| Message ID | 20221208201401.530555-1-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 |
| Headers | show |
| Series | [1/5] arm64: dts: qcom: sm6115: Fix UFS node | expand |
On 12/8/22 22:13, Konrad Dybcio wrote: > In its current form, UFS did not even probe successfully - it failed > when trying to set XO (ref_clk) to 300 MHz instead of doing so to > the ICE clk. Moreover, the missing reg-names prevented ICE from > working or being discovered at all. Fix both of these issues. > > As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0. > > Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [for the whole series] Reviewed-by: Iskren Chernev <me@iskren.info> > --- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 572bf04adf90..3f4017bc667d 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -704,6 +704,7 @@ opp-202000000 { > ufs_mem_hc: ufs@4804000 { > compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > reg = <0x04804000 0x3000>, <0x04810000 0x8000>; > + reg-names = "std", "ice"; > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > phys = <&ufs_mem_phy_lanes>; > phy-names = "ufsphy"; > @@ -736,10 +737,10 @@ ufs_mem_hc: ufs@4804000 { > <0 0>, > <0 0>, > <37500000 150000000>, > - <75000000 300000000>, > <0 0>, > <0 0>, > - <0 0>; > + <0 0>, > + <75000000 300000000>; > > status = "disabled"; > };
On Thu, 8 Dec 2022 21:13:57 +0100, Konrad Dybcio wrote: > In its current form, UFS did not even probe successfully - it failed > when trying to set XO (ref_clk) to 300 MHz instead of doing so to > the ICE clk. Moreover, the missing reg-names prevented ICE from > working or being discovered at all. Fix both of these issues. > > As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0. > > [...] Applied, thanks! [1/5] arm64: dts: qcom: sm6115: Fix UFS node commit: 01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 [2/5] arm64: dts: qcom: sm6115: Provide xo clk to rpmcc commit: ad9514be8ddb9d3a8c262aa415c2f1c1f4cc97f9 [3/5] arm64: dts: qcom: sm6115: Provide real SMD RPM XO to SDC1/2 commit: 0f1619aa22cd78a47522008e9b83524eae6bb922 [4/5] dt-bindings: arm: qcom: Add SM6115(P) and Lenovo Tab P11 commit: 92ad27fb925943d62deaaa659931ce85ddec99c8 [5/5] arm64: dts: qcom: Add Lenovo Tab P11 (J606F/XiaoXin Pad) dts commit: 67e75cfea375b5eca42a8d41b927fa195e723fe6 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf90..3f4017bc667d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -704,6 +704,7 @@ opp-202000000 { ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -736,10 +737,10 @@ ufs_mem_hc: ufs@4804000 { <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; };
In its current form, UFS did not even probe successfully - it failed when trying to set XO (ref_clk) to 300 MHz instead of doing so to the ICE clk. Moreover, the missing reg-names prevented ICE from working or being discovered at all. Fix both of these issues. As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)