diff mbox series

[3/5] arm64: dts: qcom: sm6115: Provide real SMD RPM XO to SDC1/2

Message ID 20221208201401.530555-3-konrad.dybcio@linaro.org (mailing list archive)
State Accepted
Commit 0f1619aa22cd78a47522008e9b83524eae6bb922
Headers show
Series [1/5] arm64: dts: qcom: sm6115: Fix UFS node | expand

Commit Message

Konrad Dybcio Dec. 8, 2022, 8:13 p.m. UTC 
Since we have a functioning RPM clock driver, let's make use of it
and provide the real XO clock to clients, instead of the fixed-clock
stub.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6115.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 81523ab7ff60..0c6d57a17bfc 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -650,7 +650,7 @@  sdhc_1: mmc@4744000 {
 
 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 				 <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&xo_board>,
+				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
 				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
 			clock-names = "iface", "core", "xo", "ice";
 
@@ -671,7 +671,9 @@  sdhc_2: mmc@4784000 {
 				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>;
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
 			clock-names = "iface", "core", "xo";
 
 			pinctrl-0 = <&sdc2_state_on>;