| Message ID | 20221213002423.259039-8-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | SM8[12]50 GPU speedbin | expand |
On 2022-12-13 01:24:23, Konrad Dybcio wrote: > SM8250 has (at least) four GPU speed bins. With the support added on the > driver side, wire up bin detection in the DTS to restrict lower-quality > SKUs from running at frequencies they were not validated at. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7) Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index c008f49b5852..0c4ecdab1244 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -955,6 +955,18 @@ ipcc: mailbox@408000 { > #mbox-cells = <2>; > }; > > + qfprom: efuse@784000 { > + compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; > + reg = <0 0x00784000 0 0x8ff>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + gpu_speed_bin: gpu_speed_bin@19b { > + reg = <0x19b 0x1>; > + bits = <5 3>; > + }; > + }; > + > rng: rng@793000 { > compatible = "qcom,prng-ee"; > reg = <0 0x00793000 0 0x1000>; > @@ -2563,49 +2575,58 @@ gpu: gpu@3d00000 { > > qcom,gmu = <&gmu>; > > + nvmem-cells = <&gpu_speed_bin>; > + nvmem-cell-names = "speed_bin"; > + > status = "disabled"; > > zap-shader { > memory-region = <&gpu_mem>; > }; > > - /* note: downstream checks gpu binning for 670 Mhz */ > gpu_opp_table: opp-table { > compatible = "operating-points-v2"; > > opp-670000000 { > opp-hz = /bits/ 64 <670000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + opp-supported-hw = <0x6>; > }; > > opp-587000000 { > opp-hz = /bits/ 64 <587000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + opp-supported-hw = <0x7>; > }; > > opp-525000000 { > opp-hz = /bits/ 64 <525000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; > + opp-supported-hw = <0xf>; > }; > > opp-490000000 { > opp-hz = /bits/ 64 <490000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + opp-supported-hw = <0xf>; > }; > > opp-441600000 { > opp-hz = /bits/ 64 <441600000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; > + opp-supported-hw = <0xf>; > }; > > opp-400000000 { > opp-hz = /bits/ 64 <400000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + opp-supported-hw = <0xf>; > }; > > opp-305000000 { > opp-hz = /bits/ 64 <305000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + opp-supported-hw = <0xf>; > }; > }; > }; > -- > 2.39.0 >
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c008f49b5852..0c4ecdab1244 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -955,6 +955,18 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@19b { + reg = <0x19b 0x1>; + bits = <5 3>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; @@ -2563,49 +2575,58 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; - /* note: downstream checks gpu binning for 670 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-670000000 { opp-hz = /bits/ 64 <670000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-supported-hw = <0x6>; }; opp-587000000 { opp-hz = /bits/ 64 <587000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-supported-hw = <0x7>; }; opp-525000000 { opp-hz = /bits/ 64 <525000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-supported-hw = <0xf>; }; opp-490000000 { opp-hz = /bits/ 64 <490000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-supported-hw = <0xf>; }; opp-441600000 { opp-hz = /bits/ 64 <441600000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + opp-supported-hw = <0xf>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-supported-hw = <0xf>; }; opp-305000000 { opp-hz = /bits/ 64 <305000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-supported-hw = <0xf>; }; }; };
SM8250 has (at least) four GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)