| Message ID | 20221216231528.1268447-3-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sm6125: Enable GPI DMA | expand |
On 17.12.2022 00:15, Marijn Suijten wrote: > From: Martin Botka <martin.botka@somainline.org> > > Add nodes for GPI DMA hosts on SM6125. > > Signed-off-by: Martin Botka <martin.botka@somainline.org> > [Marijn: reorder properties, use sdm845 fallback compatible, disable by > default, use 3 instead of 5 dma cells] > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 37 ++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index a205121ab4a7..abcd634c4f6d 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -5,6 +5,7 @@ > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > +#include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/power/qcom-rpmpd.h> > @@ -510,6 +511,42 @@ sdhc_2: mmc@4784000 { > status = "disabled"; > }; > > + gpi_dma0: dma-controller@4a00000 { > + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; > + reg = <0x04a00000 0x60000>; > + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <8>; > + dma-channel-mask = <0x1f>; > + iommus = <&apps_smmu 0x0136 0x0>; The stream id does not need the leading zero. You made the mask a decimal zero in the previous patchset, please decide on one convention. Masks are generally more useful as hex, but for zero values I suppose zero is less noise for the same thing.. The DMA nodes however, look good otherwise. Konrad > + #dma-cells = <3>; > + status = "disabled"; > + }; > + > + gpi_dma1: dma-controller@4c00000 { > + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; > + reg = <0x04c00000 0x60000>; > + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <8>; > + dma-channel-mask = <0x0f>; > + iommus = <&apps_smmu 0x0156 0x0>; > + #dma-cells = <3>; > + status = "disabled"; > + }; > + > usb3: usb@4ef8800 { > compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; > reg = <0x04ef8800 0x400>;
On 2022-12-17 15:35:18, Konrad Dybcio wrote: > > > On 17.12.2022 00:15, Marijn Suijten wrote: > > From: Martin Botka <martin.botka@somainline.org> > > > > Add nodes for GPI DMA hosts on SM6125. > > > > Signed-off-by: Martin Botka <martin.botka@somainline.org> > > [Marijn: reorder properties, use sdm845 fallback compatible, disable by > > default, use 3 instead of 5 dma cells] > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 37 ++++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > index a205121ab4a7..abcd634c4f6d 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > @@ -5,6 +5,7 @@ > > > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > > #include <dt-bindings/clock/qcom,rpmcc.h> > > +#include <dt-bindings/dma/qcom-gpi.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/power/qcom-rpmpd.h> > > @@ -510,6 +511,42 @@ sdhc_2: mmc@4784000 { > > status = "disabled"; > > }; > > > > + gpi_dma0: dma-controller@4a00000 { > > + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; > > + reg = <0x04a00000 0x60000>; > > + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; > > + dma-channels = <8>; > > + dma-channel-mask = <0x1f>; > > + iommus = <&apps_smmu 0x0136 0x0>; > The stream id does not need the leading zero. Good catch! Will clean this up for V2. > You made the mask a decimal zero in the previous patchset, please > decide on one convention. Masks are generally more useful as hex, > but for zero values I suppose zero is less noise for the same thing.. The _vast majority_ of qcom dts uses 0x0, I'll fix that in the previous patch series. Looks like I did even clean that up when directly transplanting that patch ("Add apps_smmu with streamID to SDHCI 1/2 nodes") to sm6350 even... > The DMA nodes however, look good otherwise. And they work great, too! - Marijn
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a205121ab4a7..abcd634c4f6d 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -510,6 +511,42 @@ sdhc_2: mmc@4784000 { status = "disabled"; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04a00000 0x60000>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x0136 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04c00000 0x60000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x0f>; + iommus = <&apps_smmu 0x0156 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb3: usb@4ef8800 { compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>;