| Message ID | 20221216234027.539917-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format | expand |
On 17/12/2022 00:40, Dmitry Baryshkov wrote: > Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format > from the text description. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++ > .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- > 2 files changed, 87 insertions(+), 42 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml > delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > > diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml > new file mode 100644 > index 000000000000..497850a5b428 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm PCIe2 PHY controller > + > +maintainers: > + - Vinod Koul <vkoul@kernel.org> > + > +description: > + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm > + platforms. > + > +properties: > + compatible: > + items: > + - const: qcom,qcs404-pcie2-phy > + - const: qcom,pcie2-phy > + > + reg: > + items: > + - description: PHY register set > + > + clocks: > + items: > + - description: a clock-specifier pair for the "pipe" clock > + > + "#phy-cells": > + const: 0 > + > + vdda-vp-supply: > + description: phandle to low voltage regulator Drop "phandle to" > + > + vdda-vph-supply: > + description: phandle to high voltage regulator Drop "phandle to" > + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: phy > + - const: pipe Blank line > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 Maybe keep both next to "clocks"? And same order in "required:". > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - vdda-vp-supply > + - vdda-vph-supply > + - resets > + - reset-names > + - clock-output-names > + - "#clock-cells" > + Best regards, Krzysztof
On Sat, 17 Dec 2022 01:40:25 +0200, Dmitry Baryshkov wrote: > Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format > from the text description. > > Applied, thanks! [3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider commit: 977e9262c3542e87b513d4dad4c57b2c85e16c8c Best regards,
diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..497850a5b428 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: phandle to low voltage regulator + + vdda-vph-supply: + description: phandle to high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + - clock-output-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcs404.h> + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... + diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - };
Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format from the text description. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++ .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- 2 files changed, 87 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt