[11/15] clk: qcom: gcc-qcs404: sort out the cxo clock

Message ID	20221217001730.540502-12-dmitry.baryshkov@linaro.org (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-arm-msm-owner@kernel.org> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Taniya Das <quic_tdas@quicinc.com> Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 11/15] clk: qcom: gcc-qcs404: sort out the cxo clock Date: Sat, 17 Dec 2022 02:17:26 +0200 Message-Id: <20221217001730.540502-12-dmitry.baryshkov@linaro.org> In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	clk: qcom: gcc-qcs404: convert to parent_data \| expand [00/15] clk: qcom: gcc-qcs404: convert to parent_data [01/15] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries [02/15] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml [03/15] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 [04/15] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents [05/15] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents [06/15] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents [07/15] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock [08/15] clk: qcom: gcc-qcs404: get rid of the test clock [09/15] clk: qcom: gcc-qcs404: move PLL clocks up [10/15] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names [11/15] clk: qcom: gcc-qcs404: sort out the cxo clock [12/15] clk: qcom: gcc-qcs404: add support for GDSCs [13/15] arm64: dts: qcom: qcs404: use symbol names for PCIe resets [14/15] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node [15/15] arm64: dts: qcom: qcs404: add clocks to the gcc node

Message ID

20221217001730.540502-12-dmitry.baryshkov@linaro.org (mailing list archive)

State

Superseded

Headers

From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org
Subject: [PATCH 11/15] clk: qcom: gcc-qcs404: sort out the cxo clock
Date: Sat, 17 Dec 2022 02:17:26 +0200
Message-Id: <20221217001730.540502-12-dmitry.baryshkov@linaro.org>
In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org>
References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

clk: qcom: gcc-qcs404: convert to parent_data | expand

Commit Message

Dmitry Baryshkov Dec. 17, 2022, 12:17 a.m. UTC

The GCC driver registers the cxo clock as a thin wrapper around board's
xo_board clock. Nowadays we can use the xo_board directly in all the
clocks that use it. Use the fw_name "cxo" for this clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-qcs404.c | 97 +++++++++++++++--------------------
 1 file changed, 41 insertions(+), 56 deletions(-)

Comments

Konrad Dybcio Dec. 17, 2022, 3:15 p.m. UTC | #1

On 17.12.2022 01:17, Dmitry Baryshkov wrote:
> The GCC driver registers the cxo clock as a thin wrapper around board's
> xo_board clock. Nowadays we can use the xo_board directly in all the
> clocks that use it. Use the fw_name "cxo" for this clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
With/without the .index comment in 10/15:

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/gcc-qcs404.c | 97 +++++++++++++++--------------------
>  1 file changed, 41 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 3941175d73a5..8fb268671f0c 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -37,14 +37,21 @@ enum {
>  	P_XO,
>  };
>  
> +static const struct parent_map gcc_parent_map_1[] = {
> +	{ P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> +	{ .fw_name = "cxo", .name = "xo-board" },
> +};
> +
>  static struct clk_fixed_factor cxo = {
>  	.mult = 1,
>  	.div = 1,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "cxo",
> -		.parent_data = &(const struct clk_parent_data) {
> -			.name = "xo-board",
> -		},
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  		.num_parents = 1,
>  		.ops = &clk_fixed_factor_ops,
>  	},
> @@ -59,10 +66,8 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = {
>  		.enable_is_inverted = true,
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll0_sleep_clk_src",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.ops = &clk_alpha_pll_ops,
>  		},
>  	},
> @@ -77,10 +82,8 @@ static struct clk_alpha_pll gpll0_out_main = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll0_out_main",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.ops = &clk_alpha_pll_ops,
>  		},
>  	},
> @@ -95,10 +98,8 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll0_ao_out_main",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.flags = CLK_IS_CRITICAL,
>  			.ops = &clk_alpha_pll_fixed_ops,
>  		},
> @@ -113,10 +114,8 @@ static struct clk_alpha_pll gpll1_out_main = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll1_out_main",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.ops = &clk_alpha_pll_ops,
>  		},
>  	},
> @@ -146,10 +145,8 @@ static struct clk_alpha_pll gpll3_out_main = {
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll3_out_main",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.ops = &clk_alpha_pll_ops,
>  		},
>  	},
> @@ -163,10 +160,8 @@ static struct clk_alpha_pll gpll4_out_main = {
>  		.enable_mask = BIT(5),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll4_out_main",
> -			.parent_data = &(const struct clk_parent_data) {
> -				.hw = &cxo.hw,
> -			},
> -			.num_parents = 1,
> +			.parent_data = gcc_parent_data_1,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  			.ops = &clk_alpha_pll_ops,
>  		},
>  	},
> @@ -182,10 +177,8 @@ static struct clk_pll gpll6 = {
>  	.status_bit = 17,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gpll6",
> -		.parent_data = &(const struct clk_parent_data) {
> -			.hw = &cxo.hw,
> -		},
> -		.num_parents = 1,
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
>  		.ops = &clk_pll_ops,
>  	},
>  };
> @@ -209,23 +202,15 @@ static const struct parent_map gcc_parent_map_0[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_0[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_ao_0[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_ao_out_main.clkr.hw },
>  };
>  
> -static const struct parent_map gcc_parent_map_1[] = {
> -	{ P_XO, 0 },
> -};
> -
> -static const struct clk_parent_data gcc_parent_data_1[] = {
> -	{ .hw = &cxo.hw },
> -};
> -
>  static const struct parent_map gcc_parent_map_2[] = {
>  	{ P_XO, 0 },
>  	{ P_GPLL0_OUT_MAIN, 1 },
> @@ -234,7 +219,7 @@ static const struct parent_map gcc_parent_map_2[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_2[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	{ .hw = &gpll6_out_aux.hw },
>  	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
> @@ -247,7 +232,7 @@ static const struct parent_map gcc_parent_map_3[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_3[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	{ .hw = &gpll6_out_aux.hw },
>  };
> @@ -258,7 +243,7 @@ static const struct parent_map gcc_parent_map_4[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_4[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll1_out_main.clkr.hw },
>  };
>  
> @@ -269,7 +254,7 @@ static const struct parent_map gcc_parent_map_5[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_5[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
>  	/* "gpll0_out_aux", */
>  };
> @@ -281,7 +266,7 @@ static const struct parent_map gcc_parent_map_6[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_6[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
>  	/* "gpll0_out_aux", */
>  };
> @@ -295,7 +280,7 @@ static const struct parent_map gcc_parent_map_7[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_7[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	{ .hw = &gpll3_out_main.clkr.hw },
>  	{ .hw = &gpll6_out_aux.hw },
> @@ -308,7 +293,7 @@ static const struct parent_map gcc_parent_map_8[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_8[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "hdmi_pll", .name = "hdmi_pll" },
>  };
>  
> @@ -320,7 +305,7 @@ static const struct parent_map gcc_parent_map_9[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_9[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
>  	{ .hw = &gpll6_out_aux.hw },
> @@ -332,7 +317,7 @@ static const struct parent_map gcc_parent_map_10[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_10[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
>  };
>  
> @@ -342,7 +327,7 @@ static const struct parent_map gcc_parent_map_11[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_11[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
>  };
>  
> @@ -353,7 +338,7 @@ static const struct parent_map gcc_parent_map_12[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_12[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
>  	/* "gpll0_out_aux", */
>  };
> @@ -366,7 +351,7 @@ static const struct parent_map gcc_parent_map_13[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_13[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	{ .hw = &gpll4_out_main.clkr.hw },
>  	{ .hw = &gpll6_out_aux.hw },
> @@ -379,7 +364,7 @@ static const struct parent_map gcc_parent_map_14[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_14[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	/* "gpll4_out_aux", */
>  };
> @@ -390,7 +375,7 @@ static const struct parent_map gcc_parent_map_15[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_15[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	/* "gpll0_out_aux", */
>  };
>  
> @@ -401,7 +386,7 @@ static const struct parent_map gcc_parent_map_16[] = {
>  };
>  
>  static const struct clk_parent_data gcc_parent_data_16[] = {
> -	{ .hw = &cxo.hw },
> +	{ .fw_name = "cxo", .name = "xo-board" },
>  	{ .hw = &gpll0_out_main.clkr.hw },
>  	/* "gpll0_out_aux", */
>  };

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 3941175d73a5..8fb268671f0c 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -37,14 +37,21 @@  enum {
 	P_XO,
 };
 
+static const struct parent_map gcc_parent_map_1[] = {
+	{ P_XO, 0 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+	{ .fw_name = "cxo", .name = "xo-board" },
+};
+
 static struct clk_fixed_factor cxo = {
 	.mult = 1,
 	.div = 1,
 	.hw.init = &(struct clk_init_data){
 		.name = "cxo",
-		.parent_data = &(const struct clk_parent_data) {
-			.name = "xo-board",
-		},
+		.parent_data = gcc_parent_data_1,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
 	},
@@ -59,10 +66,8 @@  static struct clk_alpha_pll gpll0_sleep_clk_src = {
 		.enable_is_inverted = true,
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll0_sleep_clk_src",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.ops = &clk_alpha_pll_ops,
 		},
 	},
@@ -77,10 +82,8 @@  static struct clk_alpha_pll gpll0_out_main = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll0_out_main",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.ops = &clk_alpha_pll_ops,
 		},
 	},
@@ -95,10 +98,8 @@  static struct clk_alpha_pll gpll0_ao_out_main = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll0_ao_out_main",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.flags = CLK_IS_CRITICAL,
 			.ops = &clk_alpha_pll_fixed_ops,
 		},
@@ -113,10 +114,8 @@  static struct clk_alpha_pll gpll1_out_main = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll1_out_main",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.ops = &clk_alpha_pll_ops,
 		},
 	},
@@ -146,10 +145,8 @@  static struct clk_alpha_pll gpll3_out_main = {
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll3_out_main",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.ops = &clk_alpha_pll_ops,
 		},
 	},
@@ -163,10 +160,8 @@  static struct clk_alpha_pll gpll4_out_main = {
 		.enable_mask = BIT(5),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll4_out_main",
-			.parent_data = &(const struct clk_parent_data) {
-				.hw = &cxo.hw,
-			},
-			.num_parents = 1,
+			.parent_data = gcc_parent_data_1,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 			.ops = &clk_alpha_pll_ops,
 		},
 	},
@@ -182,10 +177,8 @@  static struct clk_pll gpll6 = {
 	.status_bit = 17,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll6",
-		.parent_data = &(const struct clk_parent_data) {
-			.hw = &cxo.hw,
-		},
-		.num_parents = 1,
+		.parent_data = gcc_parent_data_1,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 		.ops = &clk_pll_ops,
 	},
 };
@@ -209,23 +202,15 @@  static const struct parent_map gcc_parent_map_0[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_0[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 };
 
 static const struct clk_parent_data gcc_parent_data_ao_0[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_ao_out_main.clkr.hw },
 };
 
-static const struct parent_map gcc_parent_map_1[] = {
-	{ P_XO, 0 },
-};
-
-static const struct clk_parent_data gcc_parent_data_1[] = {
-	{ .hw = &cxo.hw },
-};
-
 static const struct parent_map gcc_parent_map_2[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
@@ -234,7 +219,7 @@  static const struct parent_map gcc_parent_map_2[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_2[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	{ .hw = &gpll6_out_aux.hw },
 	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
@@ -247,7 +232,7 @@  static const struct parent_map gcc_parent_map_3[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_3[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	{ .hw = &gpll6_out_aux.hw },
 };
@@ -258,7 +243,7 @@  static const struct parent_map gcc_parent_map_4[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_4[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll1_out_main.clkr.hw },
 };
 
@@ -269,7 +254,7 @@  static const struct parent_map gcc_parent_map_5[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_5[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 	/* "gpll0_out_aux", */
 };
@@ -281,7 +266,7 @@  static const struct parent_map gcc_parent_map_6[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_6[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 	/* "gpll0_out_aux", */
 };
@@ -295,7 +280,7 @@  static const struct parent_map gcc_parent_map_7[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_7[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	{ .hw = &gpll3_out_main.clkr.hw },
 	{ .hw = &gpll6_out_aux.hw },
@@ -308,7 +293,7 @@  static const struct parent_map gcc_parent_map_8[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_8[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "hdmi_pll", .name = "hdmi_pll" },
 };
 
@@ -320,7 +305,7 @@  static const struct parent_map gcc_parent_map_9[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_9[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
 	{ .hw = &gpll6_out_aux.hw },
@@ -332,7 +317,7 @@  static const struct parent_map gcc_parent_map_10[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_10[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 };
 
@@ -342,7 +327,7 @@  static const struct parent_map gcc_parent_map_11[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_11[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
 };
 
@@ -353,7 +338,7 @@  static const struct parent_map gcc_parent_map_12[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_12[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
 	/* "gpll0_out_aux", */
 };
@@ -366,7 +351,7 @@  static const struct parent_map gcc_parent_map_13[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_13[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	{ .hw = &gpll4_out_main.clkr.hw },
 	{ .hw = &gpll6_out_aux.hw },
@@ -379,7 +364,7 @@  static const struct parent_map gcc_parent_map_14[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_14[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	/* "gpll4_out_aux", */
 };
@@ -390,7 +375,7 @@  static const struct parent_map gcc_parent_map_15[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_15[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	/* "gpll0_out_aux", */
 };
 
@@ -401,7 +386,7 @@  static const struct parent_map gcc_parent_map_16[] = {
 };
 
 static const struct clk_parent_data gcc_parent_data_16[] = {
-	{ .hw = &cxo.hw },
+	{ .fw_name = "cxo", .name = "xo-board" },
 	{ .hw = &gpll0_out_main.clkr.hw },
 	/* "gpll0_out_aux", */
 };

[11/15] clk: qcom: gcc-qcs404: sort out the cxo clock

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