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[15/15] arm64: dts: qcom: qcs404: add clocks to the gcc node

Message ID 20221217001730.540502-16-dmitry.baryshkov@linaro.org (mailing list archive)
State Superseded
Headers show
Series clk: qcom: gcc-qcs404: convert to parent_data | expand

Commit Message

Dmitry Baryshkov Dec. 17, 2022, 12:17 a.m. UTC
Populate the gcc node with the clocks and clock-names properties to
enable DT-based lookups for the parent clocks.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Konrad Dybcio Dec. 17, 2022, 3:17 p.m. UTC | #1
On 17.12.2022 01:17, Dmitry Baryshkov wrote:
> Populate the gcc node with the clocks and clock-names properties to
> enable DT-based lookups for the parent clocks.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index b72542631337..ee337a3980fa 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -731,6 +731,19 @@ gcc: clock-controller@1800000 {
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
>  
> +			clocks = <&xo_board>,
> +				 <&sleep_clk>,
> +				 <&pcie_phy>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
> +			clock-names = "cxo",
> +				      "sleep_clk",
> +				      "pcie_0_pipe_clk_src",
> +				      "dsi0pll",
> +				      "dsi0pllbyte",
> +				      "hdmi_pll";
> +
>  			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
>  			assigned-clock-rates = <19200000>;
>  		};
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index b72542631337..ee337a3980fa 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -731,6 +731,19 @@  gcc: clock-controller@1800000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <&pcie_phy>,
+				 <0>,
+				 <0>,
+				 <0>;
+			clock-names = "cxo",
+				      "sleep_clk",
+				      "pcie_0_pipe_clk_src",
+				      "dsi0pll",
+				      "dsi0pllbyte",
+				      "hdmi_pll";
+
 			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 			assigned-clock-rates = <19200000>;
 		};