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[71.184.142.128]) by smtp.gmail.com with ESMTPSA id y6-20020a05620a44c600b006fcb4e01345sm7694158qkp.24.2022.12.19.11.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 11:12:06 -0800 (PST) From: Eric Chanudet To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney , Brian Masney , Eric Chanudet Subject: [PATCH v4 3/4] arm64: dts: qcom: sa8295p-adp: use sa8540p-pmics Date: Mon, 19 Dec 2022 14:10:00 -0500 Message-Id: <20221219191000.2570545-4-echanude@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219191000.2570545-1-echanude@redhat.com> References: <20221219191000.2570545-1-echanude@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Include the dtsi to use a single pmic descriptions. Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently. Signed-off-by: Eric Chanudet Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +----------------------- 1 file changed, 1 insertion(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 84cb6f3eeb56..c8437efe8235 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -11,6 +11,7 @@ #include #include "sa8540p.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8295P ADP"; @@ -260,84 +261,6 @@ &remoteproc_nsp1 { status = "okay"; }; -&spmi_bus { - pm8450a: pmic@0 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - wakeup-source; - }; - - pm8450a_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450a_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450c: pmic@4 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450c_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450c_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450e: pmic@8 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x8 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450e_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450e_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450g: pmic@c { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0xc SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450g_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450g_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - &ufs_mem_hc { reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;