diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 8d216a3c0851..774ed1b0be10 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1119,8 +1119,60 @@ tsens: thermal-sensor@fc4a9000 {
 			compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
 			reg = <0xfc4a9000 0x1000>, /* TM */
 			      <0xfc4a8000 0x1000>; /* SROT */
-			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
-			nvmem-cell-names = "calib", "calib_backup";
+			nvmem-cells = <&tsens_mode>,
+				      <&tsens_base1>, <&tsens_base2>,
+				      <&tsens_s0_p1>, <&tsens_s0_p2>,
+				      <&tsens_s1_p1>, <&tsens_s1_p2>,
+				      <&tsens_s2_p1>, <&tsens_s2_p2>,
+				      <&tsens_s3_p1>, <&tsens_s3_p2>,
+				      <&tsens_s4_p1>, <&tsens_s4_p2>,
+				      <&tsens_s5_p1>, <&tsens_s5_p2>,
+				      <&tsens_s6_p1>, <&tsens_s6_p2>,
+				      <&tsens_s7_p1>, <&tsens_s7_p2>,
+				      <&tsens_s8_p1>, <&tsens_s8_p2>,
+				      <&tsens_s9_p1>, <&tsens_s9_p2>,
+				      <&tsens_s10_p1>, <&tsens_s10_p2>,
+				      <&tsens_use_backup>,
+				      <&tsens_mode_backup>,
+				      <&tsens_base1_backup>, <&tsens_base2_backup>,
+				      <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
+				      <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
+				      <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
+				      <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
+				      <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
+				      <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
+				      <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
+				      <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
+				      <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
+				      <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
+				      <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
+			nvmem-cell-names = "mode",
+					   "base1", "base2",
+					   "s0_p1", "s0_p2",
+					   "s1_p1", "s1_p2",
+					   "s2_p1", "s2_p2",
+					   "s3_p1", "s3_p2",
+					   "s4_p1", "s4_p2",
+					   "s5_p1", "s5_p2",
+					   "s6_p1", "s6_p2",
+					   "s7_p1", "s7_p2",
+					   "s8_p1", "s8_p2",
+					   "s9_p1", "s9_p2",
+					   "s10_p1", "s10_p2",
+					   "use_backup",
+					   "mode_backup",
+					   "base1_backup", "base2_backup",
+					   "s0_p1_backup", "s0_p2_backup",
+					   "s1_p1_backup", "s1_p2_backup",
+					   "s2_p1_backup", "s2_p2_backup",
+					   "s3_p1_backup", "s3_p2_backup",
+					   "s4_p1_backup", "s4_p2_backup",
+					   "s5_p1_backup", "s5_p2_backup",
+					   "s6_p1_backup", "s6_p2_backup",
+					   "s7_p1_backup", "s7_p2_backup",
+					   "s8_p1_backup", "s8_p2_backup",
+					   "s9_p1_backup", "s9_p2_backup",
+					   "s10_p1_backup", "s10_p2_backup";
 			#qcom,sensors = <11>;
 			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "uplow";
@@ -1137,11 +1189,209 @@ qfprom: qfprom@fc4bc000 {
 			reg = <0xfc4bc000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			tsens_calib: calib@d0 {
-				reg = <0xd0 0x18>;
+			tsens_base1: base1@d0 {
+				reg = <0xd0 0x1>;
+				bits = <0 8>;
 			};
-			tsens_backup: backup@440 {
-				reg = <0x440 0x10>;
+			tsens_s0_p1: s0_p1@d1 {
+				reg = <0xd1 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s1_p1: s1_p1@d2 {
+				reg = <0xd1 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s2_p1: s2_p1@d2 {
+				reg = <0xd2 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s3_p1: s3_p1@d3 {
+				reg = <0xd3 0x1>;
+				bits = <2 6>;
+			};
+			tsens_s4_p1: s4_p1@d4 {
+				reg = <0xd4 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s5_p1: s5_p1@d4 {
+				reg = <0xd4 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s6_p1: s6_p1@d5 {
+				reg = <0xd5 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s7_p1: s7_p1@d6 {
+				reg = <0xd6 0x1>;
+				bits = <2 6>;
+			};
+			tsens_s8_p1: s8_p1@d7 {
+				reg = <0xd7 0x1>;
+				bits = <0 6>;
+			};
+			tsens_mode: mode@d7 {
+				reg = <0xd7 0x1>;
+				bits = <6 2>;
+			};
+			tsens_s9_p1: s9_p1@d8 {
+				reg = <0xd8 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s10_p1: s10_p1@d8 {
+				reg = <0xd8 0x2>;
+				bits = <6 6>;
+			};
+			tsens_base2: base2@d9 {
+				reg = <0xd9 0x2>;
+				bits = <4 8>;
+			};
+			tsens_s0_p2: s0_p2@da {
+				reg = <0xda 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s1_p2: s1_p2@db {
+				reg = <0xdb 0x1>;
+				bits = <2 6>;
+			};
+			tsens_s2_p2: s2_p2@dc {
+				reg = <0xdc 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s3_p2: s3_p2@dc {
+				reg = <0xdc 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s4_p2: s4_p2@dd {
+				reg = <0xdd 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s5_p2: s5_p2@de {
+				reg = <0xde 0x2>;
+				bits = <2 6>;
+			};
+			tsens_s6_p2: s6_p2@df {
+				reg = <0xdf 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s7_p2: s7_p2@e0 {
+				reg = <0xe0 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s8_p2: s8_p2@e0 {
+				reg = <0xe0 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s9_p2: s9_p2@e1 {
+				reg = <0xe1 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s10_p2: s10_p2@e2 {
+				reg = <0xe2 0x2>;
+				bits = <2 6>;
+			};
+			tsens_s5_p2_backup: s5_p2_backup@e3 {
+				reg = <0xe3 0x2>;
+				bits = <0 6>;
+			};
+			tsens_mode_backup: mode_backup@e3 {
+				reg = <0xe3 0x1>;
+				bits = <6 2>;
+			};
+			tsens_s6_p2_backup: s6_p2_backup@e4 {
+				reg = <0xe4 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s7_p2_backup: s7_p2_backup@e4 {
+				reg = <0xe4 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s8_p2_backup: s8_p2_backup@e5 {
+				reg = <0xe5 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s9_p2_backup: s9_p2_backup@e6 {
+				reg = <0xe6 0x2>;
+				bits = <2 6>;
+			};
+			tsens_s10_p2_backup: s10_p2_backup@e7 {
+				reg = <0xe7 0x1>;
+				bits = <0 6>;
+			};
+			tsens_base1_backup: base1_backup@440 {
+				reg = <0x440 0x1>;
+				bits = <0 8>;
+			};
+			tsens_s0_p1_backup: s0_p1_backup@441 {
+				reg = <0x441 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s1_p1_backup: s1_p1_backup@442 {
+				reg = <0x441 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s2_p1_backup: s2_p1_backup@442 {
+				reg = <0x442 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s3_p1_backup: s3_p1_backup@443 {
+				reg = <0x443 0x1>;
+				bits = <2 6>;
+			};
+			tsens_s4_p1_backup: s4_p1_backup@444 {
+				reg = <0x444 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s5_p1_backup: s5_p1_backup@444 {
+				reg = <0x444 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s6_p1_backup: s6_p1_backup@445 {
+				reg = <0x445 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s7_p1_backup: s7_p1_backup@446 {
+				reg = <0x446 0x1>;
+				bits = <2 6>;
+			};
+			tsens_use_backup: use_backup@447 {
+				reg = <0x447 0x1>;
+				bits = <5 3>;
+			};
+			tsens_s8_p1_backup: s8_p1_backup@448 {
+				reg = <0x448 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s9_p1_backup: s9_p1_backup@448 {
+				reg = <0x448 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s10_p1_backup: s10_p1_backup@449 {
+				reg = <0x449 0x2>;
+				bits = <4 6>;
+			};
+			tsens_base2_backup: base2_backup@44a {
+				reg = <0x44a 0x2>;
+				bits = <2 8>;
+			};
+			tsens_s0_p2_backup: s0_p2_backup@44b {
+				reg = <0x44b 0x3>;
+				bits = <2 6>;
+			};
+			tsens_s1_p2_backup: s1_p2_backup@44c {
+				reg = <0x44c 0x1>;
+				bits = <0 6>;
+			};
+			tsens_s2_p2_backup: s2_p2_backup@44c {
+				reg = <0x44c 0x2>;
+				bits = <6 6>;
+			};
+			tsens_s3_p2_backup: s3_p2_backup@44d {
+				reg = <0x44d 0x2>;
+				bits = <4 6>;
+			};
+			tsens_s4_p2_backup: s4_p2_backup@44e {
+				reg = <0x44e 0x1>;
+				bits = <2 6>;
 			};
 		};
 
