From patchwork Sat Dec 24 14:17:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13081351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AC22C4332F for ; Sat, 24 Dec 2022 14:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229699AbiLXOSd (ORCPT ); Sat, 24 Dec 2022 09:18:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229485AbiLXOSd (ORCPT ); Sat, 24 Dec 2022 09:18:33 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40DA5BF51; Sat, 24 Dec 2022 06:18:32 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BOEHKE5017121; Sat, 24 Dec 2022 14:17:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=QPI7CpkeNFA37K/s5S0XM4qXRqVAmViGI/VD+Yhp8As=; b=ELcJd5umWvX6pyMYDKCF6jqNCvGskWCVALpcd+5YEIRILjVk/uut+GGZK6t0Y5giDrLr lApGMjf3hIp3KOjYYiBTfqYYba0Cw+ro/A37pcdXcauD9ksXECAiyEQIYvc/oTGGBrYu IsK2ojWh2fqqBAtMEU1X/n7LhcXFvoCj8GevHamC4tnp67KV9VOqUh73SMEzwWJ1UBOL ewcVxxkd3TCFlToOYlJ8ON6Nq8XK8H8syHo2xEUMUFrj+0fCGfhAGLA19MoXlRXzskMJ cq07ZJxHHmAfbtWrTk/9PsiYD9/Wr19UDB/E260BjD+lKno6dBT94pBCpBNJ+97Doj3w 1A== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mnrd18j0v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 24 Dec 2022 14:17:20 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BOEHJJE025679 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 24 Dec 2022 14:17:19 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 24 Dec 2022 06:17:16 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Alexander Shishkin CC: Mao Jinlong , , , , Tingwei , Yuanfang Zhang , Tao Zhang , Hao Zhang , Subject: [PATCH] coresight: cti: Add PM runtime call in enable_store Date: Sat, 24 Dec 2022 22:17:00 +0800 Message-ID: <20221224141700.20891-1-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KV26Nt-TXqsfPjBy2G7NHCkG8XcOWXKd X-Proofpoint-GUID: KV26Nt-TXqsfPjBy2G7NHCkG8XcOWXKd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-24_06,2022-12-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212240119 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When enabling CTI by writing enable sysfs node, clock for accessing CTI register won't be enabled. Device will crash due to register access issue. Add PM runtime call in enable_store to fix this issue. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6d59c815ecf5..b1ed424ae043 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, if (ret) return ret; - if (val) + if (val) { + ret = pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; ret = cti_enable(drvdata->csdev); - else + if (ret) + pm_runtime_put(dev->parent); + } else { ret = cti_disable(drvdata->csdev); + pm_runtime_put(dev->parent); + } if (ret) return ret; return size;