diff mbox series

[RFC,01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names

Message ID 20221227013225.2847382-2-dmitry.baryshkov@linaro.org (mailing list archive)
State Superseded
Headers show
Series clock: qcom: apq8084: convert to parent_data/_hws | expand

Commit Message

Dmitry Baryshkov Dec. 27, 2022, 1:32 a.m. UTC
Define clock/clock-names properties of the GCC device node to be used
on APQ8084 platform.

Note: the driver uses a single pcie_pipe clock, however most probably
there are two pipe clocks, one from each of PCIe QMP PHYs.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../bindings/clock/qcom,gcc-apq8084.yaml      | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)

Comments

Krzysztof Kozlowski Dec. 28, 2022, 10:30 a.m. UTC | #1
On 27/12/2022 02:32, Dmitry Baryshkov wrote:
> Define clock/clock-names properties of the GCC device node to be used
> on APQ8084 platform.
> 
> Note: the driver uses a single pcie_pipe clock, however most probably
> there are two pipe clocks, one from each of PCIe QMP PHYs.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/clock/qcom,gcc-apq8084.yaml      | 43 +++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> index 8ade176c24f4..02a856f14fbe 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> @@ -25,6 +25,30 @@ properties:
>    compatible:
>      const: qcom,gcc-apq8084
>  
> +  clocks:
> +    items:
> +      - description: XO source
> +      - description: Sleep clock source
> +      - description: UFS RX symbol 0 clock
> +      - description: UFS RX symbol 1 clock
> +      - description: UFS TX symbol 0 clock
> +      - description: UFS TX symbol 1 clock
> +      - description: SATA ASIC0 clock
> +      - description: SATA RX clock
> +      - description: PCIe PIPE clock
> +
> +  clock-names:
> +    items:
> +      - const: xo
> +      - const: sleep_clk
> +      - const: ufs_rx_symbol_0_clk_src
> +      - const: ufs_rx_symbol_1_clk_src
> +      - const: ufs_tx_symbol_0_clk_src
> +      - const: ufs_tx_symbol_1_clk_src
> +      - const: sata_asic0_clk
> +      - const: sata_rx_clk
> +      - const: pcie_pipe
> +
>  required:
>    - compatible
>  
> @@ -38,5 +62,24 @@ examples:
>          #clock-cells = <1>;
>          #reset-cells = <1>;
>          #power-domain-cells = <1>;
> +
> +        clocks = <&xo_board>,
> +                 <&sleep_clk>,
> +                 <&ufsphy 0>,

No IDs available yet?

Best regards,
Krzysztof
Dmitry Baryshkov Dec. 28, 2022, 8:23 p.m. UTC | #2
On 28/12/2022 12:30, Krzysztof Kozlowski wrote:
> On 27/12/2022 02:32, Dmitry Baryshkov wrote:
>> Define clock/clock-names properties of the GCC device node to be used
>> on APQ8084 platform.
>>
>> Note: the driver uses a single pcie_pipe clock, however most probably
>> there are two pipe clocks, one from each of PCIe QMP PHYs.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   .../bindings/clock/qcom,gcc-apq8084.yaml      | 43 +++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> index 8ade176c24f4..02a856f14fbe 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> @@ -25,6 +25,30 @@ properties:
>>     compatible:
>>       const: qcom,gcc-apq8084
>>   
>> +  clocks:
>> +    items:
>> +      - description: XO source
>> +      - description: Sleep clock source
>> +      - description: UFS RX symbol 0 clock
>> +      - description: UFS RX symbol 1 clock
>> +      - description: UFS TX symbol 0 clock
>> +      - description: UFS TX symbol 1 clock
>> +      - description: SATA ASIC0 clock
>> +      - description: SATA RX clock
>> +      - description: PCIe PIPE clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: xo
>> +      - const: sleep_clk
>> +      - const: ufs_rx_symbol_0_clk_src
>> +      - const: ufs_rx_symbol_1_clk_src
>> +      - const: ufs_tx_symbol_0_clk_src
>> +      - const: ufs_tx_symbol_1_clk_src
>> +      - const: sata_asic0_clk
>> +      - const: sata_rx_clk
>> +      - const: pcie_pipe
>> +
>>   required:
>>     - compatible
>>   
>> @@ -38,5 +62,24 @@ examples:
>>           #clock-cells = <1>;
>>           #reset-cells = <1>;
>>           #power-domain-cells = <1>;
>> +
>> +        clocks = <&xo_board>,
>> +                 <&sleep_clk>,
>> +                 <&ufsphy 0>,
> 
> No IDs available yet?

No. I didn't add IDs to the UFS symbol patchset. And anyway apq8084 
seems to use different amount of UFS symbol clocks (4, while other 
platforms use just 3).
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
index 8ade176c24f4..02a856f14fbe 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
@@ -25,6 +25,30 @@  properties:
   compatible:
     const: qcom,gcc-apq8084
 
+  clocks:
+    items:
+      - description: XO source
+      - description: Sleep clock source
+      - description: UFS RX symbol 0 clock
+      - description: UFS RX symbol 1 clock
+      - description: UFS TX symbol 0 clock
+      - description: UFS TX symbol 1 clock
+      - description: SATA ASIC0 clock
+      - description: SATA RX clock
+      - description: PCIe PIPE clock
+
+  clock-names:
+    items:
+      - const: xo
+      - const: sleep_clk
+      - const: ufs_rx_symbol_0_clk_src
+      - const: ufs_rx_symbol_1_clk_src
+      - const: ufs_tx_symbol_0_clk_src
+      - const: ufs_tx_symbol_1_clk_src
+      - const: sata_asic0_clk
+      - const: sata_rx_clk
+      - const: pcie_pipe
+
 required:
   - compatible
 
@@ -38,5 +62,24 @@  examples:
         #clock-cells = <1>;
         #reset-cells = <1>;
         #power-domain-cells = <1>;
+
+        clocks = <&xo_board>,
+                 <&sleep_clk>,
+                 <&ufsphy 0>,
+                 <&ufsphy 1>,
+                 <&ufsphy 2>,
+                 <&ufsphy 3>,
+                 <&sata 0>,
+                 <&sata 1>,
+                 <&pcie_phy>;
+        clock-names = "xo",
+                      "sleep_clk",
+                      "ufs_rx_symbol_0_clk_src",
+                      "ufs_rx_symbol_1_clk_src",
+                      "ufs_tx_symbol_0_clk_src",
+                      "ufs_tx_symbol_1_clk_src",
+                      "sata_asic0_clk",
+                      "sata_rx_clk",
+                      "pcie_pipe";
     };
 ...