| Message ID | 20221228133243.3052132-10-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: get rid of core_bi_pll_test_se | expand |
On 28.12.2022 14:32, Dmitry Baryshkov wrote: > The test clock apparently it's not used by anyone upstream. Remove it. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/clk/qcom/gcc-msm8998.c | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c > index 33473c52eb90..908e996841c2 100644 > --- a/drivers/clk/qcom/gcc-msm8998.c > +++ b/drivers/clk/qcom/gcc-msm8998.c > @@ -387,7 +387,6 @@ static struct clk_alpha_pll_postdiv gpll4_out_test = { > > enum { > P_AUD_REF_CLK, > - P_CORE_BI_PLL_TEST_SE, > P_GPLL0_OUT_MAIN, > P_GPLL4_OUT_MAIN, > P_PLL0_EARLY_DIV_CLK_SRC, > @@ -399,26 +398,22 @@ static const struct parent_map gcc_parent_map_0[] = { > { P_XO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_0[] = { > { .fw_name = "xo" }, > { .hw = &gpll0_out_main.clkr.hw }, > { .hw = &gpll0_out_main.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_1[] = { > { P_XO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_1[] = { > { .fw_name = "xo" }, > { .hw = &gpll0_out_main.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_2[] = { > @@ -426,7 +421,6 @@ static const struct parent_map gcc_parent_map_2[] = { > { P_GPLL0_OUT_MAIN, 1 }, > { P_SLEEP_CLK, 5 }, > { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_2[] = { > @@ -434,47 +428,40 @@ static const struct clk_parent_data gcc_parent_data_2[] = { > { .hw = &gpll0_out_main.clkr.hw }, > { .fw_name = "sleep_clk" }, > { .hw = &gpll0_out_main.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_3[] = { > { P_XO, 0 }, > { P_SLEEP_CLK, 5 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_3[] = { > { .fw_name = "xo" }, > { .fw_name = "sleep_clk" }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_4[] = { > { P_XO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > { P_GPLL4_OUT_MAIN, 5 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_4[] = { > { .fw_name = "xo" }, > { .hw = &gpll0_out_main.clkr.hw }, > { .hw = &gpll4_out_main.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_5[] = { > { P_XO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > { P_AUD_REF_CLK, 2 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_5[] = { > { .fw_name = "xo" }, > { .hw = &gpll0_out_main.clkr.hw }, > { .fw_name = "aud_ref_clk" }, > - { .fw_name = "core_bi_pll_test_se" }, > }; > > static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 33473c52eb90..908e996841c2 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -387,7 +387,6 @@ static struct clk_alpha_pll_postdiv gpll4_out_test = { enum { P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL4_OUT_MAIN, P_PLL0_EARLY_DIV_CLK_SRC, @@ -399,26 +398,22 @@ static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll0_out_main.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_1[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_2[] = { @@ -426,7 +421,6 @@ static const struct parent_map gcc_parent_map_2[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_SLEEP_CLK, 5 }, { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_2[] = { @@ -434,47 +428,40 @@ static const struct clk_parent_data gcc_parent_data_2[] = { { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "sleep_clk" }, { .hw = &gpll0_out_main.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_3[] = { { P_XO, 0 }, { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "xo" }, { .fw_name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_4[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_4[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_AUD_REF_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "aud_ref_clk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-msm8998.c | 13 ------------- 1 file changed, 13 deletions(-)