| Message ID | 20221231215006.211860-2-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dpu: Implement tearcheck support on INTF block | expand |
On 31/12/2022 23:50, Marijn Suijten wrote: > Neither of these SoCs has INTF0, they only have a DSI interface on index > 1. Stop enabling an interrupt that can't fire. > > Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") > Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 31.12.2022 22:50, Marijn Suijten wrote: > Neither of these SoCs has INTF0, they only have a DSI interface on index > 1. Stop enabling an interrupt that can't fire. Double space. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") > Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 2196e205efa5..9814ad52cc04 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -90,6 +90,11 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_QCM2290_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF1_INTR)) > + > #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -1884,7 +1889,7 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = { > .vbif_count = ARRAY_SIZE(sdm845_vbif), > .vbif = sdm845_vbif, > .perf = &sm6115_perf_data, > - .mdss_irqs = IRQ_SC7180_MASK, > + .mdss_irqs = IRQ_QCM2290_MASK, > }; > > static const struct dpu_mdss_cfg sm8150_dpu_cfg = { > @@ -2008,7 +2013,7 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { > .reg_dma_count = 1, > .dma_cfg = &sdm845_regdma, > .perf = &qcm2290_perf_data, > - .mdss_irqs = IRQ_SC7180_MASK, > + .mdss_irqs = IRQ_QCM2290_MASK, > }; > > static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
On 2023-01-02 10:29:03, Konrad Dybcio wrote: > > > On 31.12.2022 22:50, Marijn Suijten wrote: > > Neither of these SoCs has INTF0, they only have a DSI interface on index > > 1. Stop enabling an interrupt that can't fire. > Double space. In case you hadn't noticed I'm employing this habit for quite some time now: after ending a sentence with a period, use a double space. The likes of GKH do it too. It may look a bit off though with 1. at the beginning of the sentence resembling the start of an ordered list. - Marijn > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Konrad
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 2196e205efa5..9814ad52cc04 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -90,6 +90,11 @@ BIT(MDP_AD4_0_INTR) | \ BIT(MDP_AD4_1_INTR)) +#define IRQ_QCM2290_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR)) + #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ BIT(MDP_SSPP_TOP0_INTR2) | \ BIT(MDP_SSPP_TOP0_HIST_INTR) | \ @@ -1884,7 +1889,7 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6115_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, + .mdss_irqs = IRQ_QCM2290_MASK, }; static const struct dpu_mdss_cfg sm8150_dpu_cfg = { @@ -2008,7 +2013,7 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sdm845_regdma, .perf = &qcm2290_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, + .mdss_irqs = IRQ_QCM2290_MASK, }; static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
Neither of these SoCs has INTF0, they only have a DSI interface on index 1. Stop enabling an interrupt that can't fire. Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)