From patchwork Mon Jan 2 10:48:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13086639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 959FBC46467 for ; Mon, 2 Jan 2023 10:49:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232130AbjABKtx (ORCPT ); Mon, 2 Jan 2023 05:49:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232471AbjABKtX (ORCPT ); Mon, 2 Jan 2023 05:49:23 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFB69B25; Mon, 2 Jan 2023 02:49:22 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 302AdVmk001973; Mon, 2 Jan 2023 10:49:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=wfzCuv2Ut8akRnI/rige7c6Hypvi9XxXIunuUHzQ1N0=; b=m9ou3jZ9oxmYtKQgoRhLk5U/13X8RoxerIXzW9R962zOIdFouTKlYD10uWu14HZ3m5vq TAYXrCDRM8sklW1i8Uxo7VMcOm0SSuOdwk7eKDVei+BF5bO+tbdnR18ecukIq7UhcAQb lZtmTxX/lxIJLOZH9Je+K9RAii7TP6zRRu5LI9Dwg4Sdoxz3qkB20tjhwBqK1pvu/87F r+2eDxg4Zav+Jz2kWyHPYqeofXo/xO8NjEYUMl7udIMqPBw16NEGVuTMNIXgyv0aXYAD NCszSqicCQVKjMM91BgFbDo+JFC5dDNyj2e2zHoVLsnrcJBMk0v68YEr3nt/WKV6D1qJ LA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mtaewb31r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 02 Jan 2023 10:49:13 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 302AnC4N012728 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Jan 2023 10:49:12 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 2 Jan 2023 02:49:06 -0800 From: Akhil P Oommen To: freedreno , , , Rob Clark , Ulf Hansson , Bjorn Andersson , Stephen Boyd , Philipp Zabel CC: Akhil P Oommen , Abhinav Kumar , Chia-I Wu , Daniel Vetter , David Airlie , Dmitry Baryshkov , Douglas Anderson , Konrad Dybcio , Sean Paul , Subject: [PATCH v5 4/5] drm/msm/a6xx: Remove cx gdsc polling using 'reset' Date: Mon, 2 Jan 2023 16:18:30 +0530 Message-ID: <20230102161757.v5.4.I96e0bf9eaf96dd866111c1eec8a4c9b70fd7cbcb@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com> References: <1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fIwE4au6IqhOrhp_wSUYFIsVWKxsR_Ht X-Proofpoint-GUID: fIwE4au6IqhOrhp_wSUYFIsVWKxsR_Ht X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-02_06,2022-12-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301020098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the unused 'reset' interface which was supposed to help to ensure that cx gdsc has collapsed during gpu recovery. This is was not enabled so far due to missing gpucc driver support. Similar functionality using genpd framework will be implemented in the upcoming patch. This effectively reverts commit 1f6cca404918 ("drm/msm/a6xx: Ensure CX collapse during gpu recovery"). Signed-off-by: Akhil P Oommen Reviewed-by: Ulf Hansson Reviewed-by: Philipp Zabel --- (no changes since v3) Changes in v3: - Updated commit msg (Philipp) drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ---- drivers/gpu/drm/msm/msm_gpu.c | 4 ---- drivers/gpu/drm/msm/msm_gpu.h | 4 ---- 3 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 36c8fb699b56..4b16e75dfa50 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,7 +10,6 @@ #include #include -#include #include #define GPU_PAS_ID 13 @@ -1298,9 +1297,6 @@ static void a6xx_recover(struct msm_gpu *gpu) /* And the final one from recover worker */ pm_runtime_put_sync(&gpu->pdev->dev); - /* Call into gpucc driver to poll for cx gdsc collapse */ - reset_control_reset(gpu->cx_collapse); - pm_runtime_use_autosuspend(&gpu->pdev->dev); if (active_submits) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 30ed45af76ad..97e1319d4577 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include /* @@ -933,9 +932,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (IS_ERR(gpu->gpu_cx)) gpu->gpu_cx = NULL; - gpu->cx_collapse = devm_reset_control_get_optional_exclusive(&pdev->dev, - "cx_collapse"); - gpu->pdev = pdev; platform_set_drvdata(pdev, &gpu->adreno_smmu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 651786bc55e5..fa9e34d02c91 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -13,7 +13,6 @@ #include #include #include -#include #include "msm_drv.h" #include "msm_fence.h" @@ -282,9 +281,6 @@ struct msm_gpu { bool hw_apriv; struct thermal_cooling_device *cooling; - - /* To poll for cx gdsc collapse during gpu recovery */ - struct reset_control *cx_collapse; }; static inline struct msm_gpu *dev_to_gpu(struct device *dev)