[01/21] clk: qcom: dispcc-sm8450: switch to parent_hws

Message ID	20230103145515.1164020-2-dmitry.baryshkov@linaro.org (mailing list archive)
State	Accepted
Commit	5c0df30cb3e431b9bcc10b457bb9fda388842035
Headers	show Return-Path: <linux-arm-msm-owner@vger.kernel.org> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Taniya Das <quic_tdas@quicinc.com> Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 01/21] clk: qcom: dispcc-sm8450: switch to parent_hws Date: Tue, 3 Jan 2023 16:54:55 +0200 Message-Id: <20230103145515.1164020-2-dmitry.baryshkov@linaro.org> In-Reply-To: <20230103145515.1164020-1-dmitry.baryshkov@linaro.org> References: <20230103145515.1164020-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	clk: qcom: small cleanup \| expand [00/21] clk: qcom: small cleanup [01/21] clk: qcom: dispcc-sm8450: switch to parent_hws [02/21] clk: qcom: dispcc-sc7180: switch to parent_hws [03/21] clk: qcom: dispcc-sm6375: switch to parent_hws [04/21] clk: qcom: camcc-sc7280: switch to parent_hws [05/21] clk: qcom: camcc-sm8450: switch to parent_hws [06/21] clk: qcom: gcc-msm8939: switch to parent_hws [07/21] clk: qcom: gcc-msm8976: switch to parent_hws [08/21] clk: qcom: gcc-sc7180: switch to parent_hws [09/21] clk: qcom: gcc-sc7280: switch to parent_hws [10/21] clk: qcom: gcc-sdx65: switch to parent_hws [11/21] clk: qcom: gcc-sm6375: switch to parent_hws [12/21] clk: qcom: gcc-sm8250: switch to parent_hws [13/21] clk: qcom: gcc-sm8450: switch to parent_hws [14/21] clk: qcom: gcc-sm8550: switch to parent_hws [15/21] clk: qcom: gpucc-msm8998: switch to parent_hws [16/21] clk: qcom: gpucc-sc7180: switch to parent_hws [17/21] clk: qcom: lpasscc-sc7180: switch to parent_hws [18/21] clk: qcom: dispcc-sm8250: switch to devm_pm_runtime_enable [19/21] clk: qcom: dispcc-sm8450: switch to devm_pm_runtime_enable [20/21] clk: qcom: lpasscc-sc7280: switch to devm_pm_runtime_enable [21/21] clk: qcom: videocc-sm8250: switch to devm_pm_runtime_enable

diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 0cd7ebe90301..40efa4682bed 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -694,8 +694,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -708,8 +708,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte1_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -722,8 +722,8 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -737,8 +737,8 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -752,8 +752,8 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -767,8 +767,8 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_div_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -784,8 +784,8 @@ static struct clk_branch disp_cc_mdss_ahb1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_ahb1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -802,8 +802,8 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_ahb_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -820,8 +820,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -838,8 +838,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -856,8 +856,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -874,8 +874,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte1_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -892,8 +892,8 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_aux_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -910,8 +910,8 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_crypto_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -928,8 +928,8 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -946,8 +946,8 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -964,8 +964,8 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -982,8 +982,8 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1000,8 +1000,8 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1018,8 +1018,8 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_aux_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1036,8 +1036,8 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_crypto_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1054,8 +1054,8 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1072,8 +1072,8 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1090,8 +1090,8 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1108,8 +1108,8 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1126,8 +1126,8 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1144,8 +1144,8 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_aux_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1162,8 +1162,8 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_crypto_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1180,8 +1180,8 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1198,8 +1198,8 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1216,8 +1216,8 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1234,8 +1234,8 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1252,8 +1252,8 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_aux_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1270,8 +1270,8 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_crypto_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1288,8 +1288,8 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1306,8 +1306,8 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_intf_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1324,8 +1324,8 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_pixel0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1342,8 +1342,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_esc0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1360,8 +1360,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_esc1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_esc1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_esc1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1378,8 +1378,8 @@ static struct clk_branch disp_cc_mdss_mdp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_mdp1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1396,8 +1396,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_mdp_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1414,8 +1414,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_mdp_lut1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1432,8 +1432,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_mdp_lut_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1450,8 +1450,8 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_non_gdsc_ahb_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1468,8 +1468,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_pclk0_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1486,8 +1486,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_pclk1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_pclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_pclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1504,8 +1504,8 @@ static struct clk_branch disp_cc_mdss_rot1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_rot1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1522,8 +1522,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_rot_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1540,8 +1540,8 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_rscc_ahb_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1558,8 +1558,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1576,8 +1576,8 @@ static struct clk_branch disp_cc_mdss_vsync1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_vsync1_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1594,8 +1594,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_vsync_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1612,8 +1612,8 @@ static struct clk_branch disp_cc_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "disp_cc_sleep_clk", - .parent_data = &(const struct clk_parent_data) { - .hw = &disp_cc_sleep_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_sleep_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT,

[01/21] clk: qcom: dispcc-sm8450: switch to parent_hws

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