From patchwork Thu Jan 5 13:41:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13089913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A17F7C63705 for ; Thu, 5 Jan 2023 13:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232650AbjAENln (ORCPT ); Thu, 5 Jan 2023 08:41:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232982AbjAENlk (ORCPT ); Thu, 5 Jan 2023 08:41:40 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9626834757 for ; Thu, 5 Jan 2023 05:41:38 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id g13so55047543lfv.7 for ; Thu, 05 Jan 2023 05:41:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L1M6ooEdJfvuI+Oqf5uOCpz/6BbeljR+cFweGDUslGQ=; b=fqv/5XvFeofyyXK+43k2JAHjIAkf2M2cv+HjQr0u+llcp3BcE1Ri5DHqUSa1+Vgk6f bo3TwIpkz0JOBaWc3UbwTy9FL0K+GU0W8YUF2W/reNIS3gwDH7demDoityLq/0oQf2K6 NMUAfe/pIyfvEYEmA4hEgwOCD3fVcIVcJfD8xxndsNtUGUFpiDFKifdfpZY+BKpB5mdo ovbKCs6G4/ndlS2QFe2lpBQwar+1XdLIR2TzvjKTPYaGj/hh8G1GvbVB5whiY8fh+ggf Ti/gAM3XToL0YZ4QsoRTkYVHPAHZbo/irQng9mJ+MjPe6FsL0HnwO+00FOrGEi+Jfx8l dj4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L1M6ooEdJfvuI+Oqf5uOCpz/6BbeljR+cFweGDUslGQ=; b=6mJJvtqwM9u1PHYXCixYCZ7irbBoQdBP4nEKk8LlUuvApY8A+zGp3zkB569d2/HUWC kc4Xbq397x3EDr+o6RoyDxXrd1F5HDLUdh94iOwoElRclFVnzrAjynH5LLGzpMZdsbCu vkaBiItE2fzAFqdfWLt4Pm3bn979zKqKvmgiDSRMEvqWc+vnl3P8sh034Ew4zYj8374W qBXAWmd0ndEnLBEAmrwM29WmkEww4c5nAqli003V3yNAUl0IvkjH+dR+ckR+hLZ2Jn8U 9tURz3XgKA6En8AeHQQTPqCWrmTF1TdSxWl/ogvuqxpF0nsbVJPcD2EIMGFUYogvsUtR /pWA== X-Gm-Message-State: AFqh2kreOKjhidsfkbZQ6ODHnesA4zWqXVMUcnXpobjQR/t4B0vMCx00 ac2SpSwGMv/S8uMNLJAIbhcVig== X-Google-Smtp-Source: AMrXdXuvLb9TL2VemP8XmYa/gM3pciyLR3bo9qypurEBX8yuMsxUnV6ULHj4eE5OeKoRuX4qxK3daA== X-Received: by 2002:a05:6512:3f85:b0:4ca:e658:e40c with SMTP id x5-20020a0565123f8500b004cae658e40cmr13607431lfa.50.1672926098145; Thu, 05 Jan 2023 05:41:38 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id bq25-20020a056512151900b004b592043413sm5461315lfb.12.2023.01.05.05.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 05:41:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Date: Thu, 5 Jan 2023 15:41:26 +0200 Message-Id: <20230105134133.1550618-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105134133.1550618-1-dmitry.baryshkov@linaro.org> References: <20230105134133.1550618-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-apq8084.c | 162 ++++++++++++++++----------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index b41f55b289ae..05a68f645115 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -36,6 +36,87 @@ enum { P_SLEEP_CLK, }; +static struct clk_pll gpll0 = { + .l_reg = 0x0004, + .m_reg = 0x0008, + .n_reg = 0x000c, + .config_reg = 0x0014, + .mode_reg = 0x0000, + .status_reg = 0x001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_vote", + .parent_names = (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll1 = { + .l_reg = 0x0044, + .m_reg = 0x0048, + .n_reg = 0x004c, + .config_reg = 0x0054, + .mode_reg = 0x0040, + .status_reg = 0x005c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll1_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_vote", + .parent_names = (const char *[]){ "gpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_xo_gpll0_map[] = { { P_XO, 0 }, { P_GPLL0, 1 } @@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = { "sleep_clk_src", }; -static struct clk_pll gpll0 = { - .l_reg = 0x0004, - .m_reg = 0x0008, - .n_reg = 0x000c, - .config_reg = 0x0014, - .mode_reg = 0x0000, - .status_reg = 0x001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll0_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_vote", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = { }, }; -static struct clk_pll gpll1 = { - .l_reg = 0x0044, - .m_reg = 0x0048, - .n_reg = 0x004c, - .config_reg = 0x0054, - .mode_reg = 0x0040, - .status_reg = 0x005c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll1_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_vote", - .parent_names = (const char *[]){ "gpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = { F(100000000, P_GPLL0, 6, 0, 0), F(200000000, P_GPLL0, 3, 0, 0),