From patchwork Wed Jan 11 06:03:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13096086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D8BC63797 for ; Wed, 11 Jan 2023 06:04:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233363AbjAKGEZ (ORCPT ); Wed, 11 Jan 2023 01:04:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232465AbjAKGEP (ORCPT ); Wed, 11 Jan 2023 01:04:15 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10201B874 for ; Tue, 10 Jan 2023 22:04:09 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id g13so21941472lfv.7 for ; Tue, 10 Jan 2023 22:04:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L1M6ooEdJfvuI+Oqf5uOCpz/6BbeljR+cFweGDUslGQ=; b=Oii50Um1hWkieumYjqmCSJNv444oiiAhCr6w080On9ENIk4gqTyNdwmZRWGsCO/TqR pxNWiIYCP1NUrFfiDG20Xuygbef566PAX/e0BnGEYZ27adpwl/8YVVQMSkmhPLtZruYc 8fsFpvaoWPo+bHgNIPMx5COQ3MFGBctLWTFvvYX6CTRxhquaQAsImqxjieGwadNL3va4 0ePByhvV7nMSRVaGBtU8IRSPmK6UhcZdcEWlcNdtpBvXBmtdu9QYpSBvlGoUr2FGWGf9 rZ6FIfWbju8ogduaoVmlSJxmgMdA4F6ger0V9F95tszCj4y+e0ciRJwP3E8ZGsIXfYvO cZMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L1M6ooEdJfvuI+Oqf5uOCpz/6BbeljR+cFweGDUslGQ=; b=n0e631CVZ34SlGQTbMw6LAfyEN42pCK4xkuE7BQrMYFDhgifssgJpbJrsg+K3Myxqz /ldfNGY62iAFT/VM5gz0Rj/bKHeNIJXzPOPm3G3eXQeoCUwn1VH7qpVgdAMERBQX3XAZ uF8L95REEJwOxAnYux/xfhUoDhD/7bmelRv5TYdp1yVH+qqCLycop2qeBeFnQq7AcJvK R+ZvQCRZ4eBh/4ec6ibp70/SuZHR5WWiYhfVeN4Nl/D8uXmO0/6KNx2SyItMynbQotvH 5mrFVM40nrOUw+PS1Uu1WtfMin/wWEqJgmOwW65hi8CpbbYZiTHOO8BRo1Kusy6QcgXn 19NA== X-Gm-Message-State: AFqh2kpMPNjxmlD9UvCPt/jfZFt9U3wF6iVEptDTTsduCk3dENjyYBgn OD54o1Pb802raOjYhmhxQmz6xw== X-Google-Smtp-Source: AMrXdXuA3/iPPESq9Ea6jp6oBGlEiOKzEYwPIfMOA4ZbqMzK8QXhujNvsl0qs1VL309V+OGPyhxZhw== X-Received: by 2002:ac2:5d4e:0:b0:4b3:f50c:69a8 with SMTP id w14-20020ac25d4e000000b004b3f50c69a8mr20547935lfd.47.1673417047345; Tue, 10 Jan 2023 22:04:07 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id b7-20020a056512070700b004cb143f7391sm2524607lfs.258.2023.01.10.22.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 22:04:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Date: Wed, 11 Jan 2023 08:03:55 +0200 Message-Id: <20230111060402.1168726-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111060402.1168726-1-dmitry.baryshkov@linaro.org> References: <20230111060402.1168726-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/clk/qcom/gcc-apq8084.c | 162 ++++++++++++++++----------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index b41f55b289ae..05a68f645115 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -36,6 +36,87 @@ enum { P_SLEEP_CLK, }; +static struct clk_pll gpll0 = { + .l_reg = 0x0004, + .m_reg = 0x0008, + .n_reg = 0x000c, + .config_reg = 0x0014, + .mode_reg = 0x0000, + .status_reg = 0x001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_vote", + .parent_names = (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll1 = { + .l_reg = 0x0044, + .m_reg = 0x0048, + .n_reg = 0x004c, + .config_reg = 0x0054, + .mode_reg = 0x0040, + .status_reg = 0x005c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll1_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_vote", + .parent_names = (const char *[]){ "gpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_xo_gpll0_map[] = { { P_XO, 0 }, { P_GPLL0, 1 } @@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = { "sleep_clk_src", }; -static struct clk_pll gpll0 = { - .l_reg = 0x0004, - .m_reg = 0x0008, - .n_reg = 0x000c, - .config_reg = 0x0014, - .mode_reg = 0x0000, - .status_reg = 0x001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll0_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_vote", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = { }, }; -static struct clk_pll gpll1 = { - .l_reg = 0x0044, - .m_reg = 0x0048, - .n_reg = 0x004c, - .config_reg = 0x0054, - .mode_reg = 0x0040, - .status_reg = 0x005c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll1_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_vote", - .parent_names = (const char *[]){ "gpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = { F(100000000, P_GPLL0, 6, 0, 0), F(200000000, P_GPLL0, 3, 0, 0),