From patchwork Tue Jan 17 12:55:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13104614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96D7DC63797 for ; Tue, 17 Jan 2023 12:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236995AbjAQM4L (ORCPT ); Tue, 17 Jan 2023 07:56:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236919AbjAQM4H (ORCPT ); Tue, 17 Jan 2023 07:56:07 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91D212E0F5 for ; Tue, 17 Jan 2023 04:56:05 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id m15so965865wms.4 for ; Tue, 17 Jan 2023 04:56:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m0J4ixIsmD84QvxlmKW/mg66A7OhRu7p2ER1fOK4keg=; b=M3sUT5w+rom8V8hCC+2ieLE6cdT8uXbHUFMOzd0c3mFch9qLpkVXzyeC7UHivXo3fI +7/q4GhA35fD7Oar2s97+BEN+SmRgpgEQH59nLLmfdwTeiHEPHUC4TygZvL7gTYPmgkL YvwbIeBenZCkSpIW6r1mqIzaCtoMGDPAFOaRT7eTtJiVL2xAJJ9GTNghZf7C2TRF1cCN gRYHKT+KpRCy8Ve64AT0hGyfvUaH4hX08D61vZC6QcT3bC4Y/dI8xdZxhBZjQQ/YC01o GnTFdulm8boBH/odok/ily63KjFytYCLPSs0MFlGAUpKqpopcJRPNnNWTy8eRC3tmIeo NDiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m0J4ixIsmD84QvxlmKW/mg66A7OhRu7p2ER1fOK4keg=; b=gfiNqPR1yNIyKMY1/8LRV+YZOnVjnKuo23uzeWIi9C82yrGgIDF4HUzuJ6QIC0Irap ZTb8nMYUen4ailTkbWwjF914DNtG3jz2sapPhJqLMOMob50Zjq7YwKiH5uC0caPGVpDT 9x+5Uq3qDeNBQ+bmPp1atQLoKk0fjx6QIrCcmDu/bX2jBC+ujZS1eUyVleDR+MQjOoGa sQlktpFXjFaZFNlvw42lge1UmXXAXqCNQdROny8om9Fx6ctyUB2gYY+XBsslj3JfJ20+ uovFumEdcImNSxY7/C1H7LNneHFa1zlwefBNGdfF+9YruWO3hjXlM0K2yXFpgEsAVr7p mD2g== X-Gm-Message-State: AFqh2kr4XMIbETGs3GtDVlOGJo4WZQ8aujvaQxDJPdCeQ1GHAvE6cYNj YvQeuHbqyA/G+wd679CDgfxlDA== X-Google-Smtp-Source: AMrXdXvp72Gltc+7kuQmm2hYP4i0bN/Ac2rb5sYqJtsMDr3jNk/DViNanc9vE4x20HsVHQY5UxosEg== X-Received: by 2002:a05:600c:4928:b0:3d9:a5a2:65fa with SMTP id f40-20020a05600c492800b003d9a5a265famr2928801wmp.7.1673960164145; Tue, 17 Jan 2023 04:56:04 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id g12-20020a05600c310c00b003c70191f267sm45069778wmo.39.2023.01.17.04.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 04:56:03 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Johan Hovold Subject: [PATCH v3 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets Date: Tue, 17 Jan 2023 14:55:51 +0200 Message-Id: <20230117125555.163087-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117125555.163087-1-abel.vesa@linaro.org> References: <20230117125555.163087-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa --- .../qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 82 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + 2 files changed, 84 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h new file mode 100644 index 000000000000..f420f8faf16a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V6_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V6_H_ + +/* Only for QMP V6 PHY - QSERDES COM registers */ + +#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V6_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V6_COM_DEC_START_MODE1 0x28 +#define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c +#define QSERDES_V6_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48 +#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c +#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V6_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V6_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V6_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0 0x7c +#define QSERDES_V6_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V6_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V6_COM_DEC_START_MODE0 0x88 +#define QSERDES_V6_COM_DEC_START_MSB_MODE0 0x8c +#define QSERDES_V6_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V6_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V6_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1 0x9c +#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0 0xa0 +#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0 0xa4 +#define QSERDES_V6_COM_VCO_TUNE1_MODE0 0xa8 +#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac +#define QSERDES_V6_COM_BG_TIMER 0xbc +#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0 +#define QSERDES_V6_COM_SSC_PER1 0xcc +#define QSERDES_V6_COM_SSC_PER2 0xd0 +#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8 +#define QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc +#define QSERDES_V6_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8 +#define QSERDES_V6_COM_PLL_IVCO 0xf4 +#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V6_COM_RESETSM_CNTRL 0x118 +#define QSERDES_V6_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V6_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c +#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148 +#define QSERDES_V6_COM_CLK_SELECT 0x164 +#define QSERDES_V6_COM_CORE_CLK_EN 0x170 +#define QSERDES_V6_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V6_COM_SVS_MODE_CLK_SEL 0x17c +#define QSERDES_V6_COM_CMN_MISC_1 0x184 +#define QSERDES_V6_COM_CMN_MODE 0x188 +#define QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL 0x198 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac +#define QSERDES_V6_COM_ADDITIONAL_MISC 0x1b4 +#define QSERDES_V6_COM_ADDITIONAL_MISC_2 0x1b8 +#define QSERDES_V6_COM_ADDITIONAL_MISC_3 0x1bc +#define QSERDES_V6_COM_CMN_STATUS 0x1d0 +#define QSERDES_V6_COM_C_READY_STATUS 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index fd99a5d02703..d1275d20a3a3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -21,6 +21,8 @@ #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" +#include "phy-qcom-qmp-qserdes-com-v6.h" + #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h"