| Message ID | 20230201090529.30446-4-quic_poovendh@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable crashdump collection support for IPQ9574 | expand |
On 01/02/2023 09:05, Poovendhan Selvaraj wrote: > Add support to read-modify-write TCSR register to modify only DLOAD bit. > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com> > --- > drivers/firmware/qcom_scm.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > index 2000323722bf..e3435587a72d 100644 > --- a/drivers/firmware/qcom_scm.c > +++ b/drivers/firmware/qcom_scm.c > @@ -407,7 +407,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id) > } > EXPORT_SYMBOL(qcom_scm_set_remote_state); > > -static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) > +static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable) > { > struct qcom_scm_desc desc = { > .svc = QCOM_SCM_SVC_BOOT, > @@ -417,7 +417,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) > .owner = ARM_SMCCC_OWNER_SIP, > }; > > - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; > + desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; It is not read-modify-write when enable == false, its just writing 0. Is this intentional? > > return qcom_scm_call_atomic(__scm->dev, &desc, NULL); > } > @@ -426,15 +426,19 @@ static void qcom_scm_set_download_mode(bool enable) > { > bool avail; > int ret = 0; > + u32 dload_addr_val; > > avail = __qcom_scm_is_call_available(__scm->dev, > QCOM_SCM_SVC_BOOT, > QCOM_SCM_BOOT_SET_DLOAD_MODE); > + ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val); > + > if (avail) { > - ret = __qcom_scm_set_dload_mode(__scm->dev, enable); > + ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable); > } else if (__scm->dload_mode_addr) { > ret = qcom_scm_io_writel(__scm->dload_mode_addr, > - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); > + enable ? dload_addr_val | > + QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); same here. --srini > } else { > dev_err(__scm->dev, > "No available mechanism for setting download mode\n");
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 2000323722bf..e3435587a72d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -407,7 +407,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id) } EXPORT_SYMBOL(qcom_scm_set_remote_state); -static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) +static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable) { struct qcom_scm_desc desc = { .svc = QCOM_SCM_SVC_BOOT, @@ -417,7 +417,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) .owner = ARM_SMCCC_OWNER_SIP, }; - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; + desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; return qcom_scm_call_atomic(__scm->dev, &desc, NULL); } @@ -426,15 +426,19 @@ static void qcom_scm_set_download_mode(bool enable) { bool avail; int ret = 0; + u32 dload_addr_val; avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE); + ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val); + if (avail) { - ret = __qcom_scm_set_dload_mode(__scm->dev, enable); + ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable); } else if (__scm->dload_mode_addr) { ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + enable ? dload_addr_val | + QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n");