| Message ID | 20230202104452.299048-11-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 272fc52431611d779de132c4e03de6e0c1199731 |
| Headers | show |
| Series | pinctrl/ARM/arm64: qcom: correct TLMM gpio-ranges and GPIO pin names | expand |
On 2/2/23 12:44, Krzysztof Kozlowski wrote: > Correct the number of GPIOs in TLMM pin controller. > > Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> > --- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 50cb8a82ecd5..b9fff0b0ea1c 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -363,7 +363,7 @@ tlmm: pinctrl@500000 { > reg-names = "west", "south", "east"; > interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > gpio-controller; > - gpio-ranges = <&tlmm 0 0 121>; > + gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 50cb8a82ecd5..b9fff0b0ea1c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -363,7 +363,7 @@ tlmm: pinctrl@500000 { reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&tlmm 0 0 121>; + gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>;
Correct the number of GPIOs in TLMM pin controller. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)