From patchwork Mon Feb 6 21:26:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13130666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3607C64EC4 for ; Mon, 6 Feb 2023 21:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230189AbjBFV0o (ORCPT ); Mon, 6 Feb 2023 16:26:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbjBFV0g (ORCPT ); Mon, 6 Feb 2023 16:26:36 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7417B2ED5E for ; Mon, 6 Feb 2023 13:26:31 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id h16so11718634wrz.12 for ; Mon, 06 Feb 2023 13:26:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YMHYSZY5yr6WJXzgdfqkly/OyevTb2bnXVt/gz3eRFM=; b=MsZ8JkPs5eVvQswJTnLchlAbu12udviEsdo4ZP+lL7Zv0B/lHeyPzSpkAtoPwViyN0 bgfyuHztJtde0y1Bnq6M84UftsSX+yqhq05Wmi3vNVPiMjBHFM1rsQc3vrM+3GyJ5Nih IGIeWFHJezisxIVaMGAWk9y6pFHOijIvJDWS8d+ndEL5nAKx0Rij50+Vgajw8oMkby9z xyStj4vgdlGnl5scsEoxkYIp9A0eKKrMRNZFYHDjFL8WIjmVjc7CNUu9tatJLfLoFj/L MRedcmJJfoAhye8zNuk90DAuipp5JMczO48Bks9nlwFJ8RDHxFAlop0fhouc+B9snwHo SG9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YMHYSZY5yr6WJXzgdfqkly/OyevTb2bnXVt/gz3eRFM=; b=n660JsG+3YsVdprfx3swC7zzH41jOPn3SaZg4II8FotTLbFTWZwj5DLhp14Zp/H2Xh Nl1U03CxCn6Il51tjKUGWTgdSWz/6DjmvxVVGfgKFkoLl4dcUQSAMfcVVHoI9KD1H7vL 3e/Z3EVj1N8mSKVM5WxZJoIBxzOIQ8tvZDmmw7q0hFG4Rg2RYh19Naw8jQ/EYlEGTZXU um59t7Guhu9uAAD/l9QeplRLtBs6Nn1uFROrNHAjZ7BQaWmMochp6O6SeO9l1MZ36oqM PK8OW6QdqoUzUudPXqtr88oQABzXFYRwFqryWhFfaSONEmNHgllbK+vl6gf7cG/pCY0M 8esA== X-Gm-Message-State: AO0yUKVwVtfJkcrTNi/GsT3J8iIj4HgItEZP9ieG1B0EFMe6V2Roc7ff eG2WKsoTWDYeo3S+OlRDSk2Rzw== X-Google-Smtp-Source: AK7set/DKvfsz5pRDGq06xNJlM0WynrXe2RNjIsV4ZKhzkTx8cPmEhGCSyOMwOFsEhXiONOjkd7SVw== X-Received: by 2002:adf:f4cf:0:b0:2bf:c066:dd7e with SMTP id h15-20020adff4cf000000b002bfc066dd7emr283641wrp.40.1675718790936; Mon, 06 Feb 2023 13:26:30 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id j11-20020a5d604b000000b002b57bae7174sm9783341wrt.5.2023.02.06.13.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 13:26:30 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v8 05/11] phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets Date: Mon, 6 Feb 2023 23:26:13 +0200 Message-Id: <20230206212619.3218741-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230206212619.3218741-1-abel.vesa@linaro.org> References: <20230206212619.3218741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- The v7 of this patch is: https://lore.kernel.org/all/20230203081807.2248625-6-abel.vesa@linaro.org/ Changes since v7: * none Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 05b59f261999..907f3f236f05 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -30,6 +30,7 @@ #include "phy-qcom-qmp-pcs-pcie-v5.h" #include "phy-qcom-qmp-pcs-pcie-v5_20.h" #include "phy-qcom-qmp-pcs-pcie-v6.h" +#include "phy-qcom-qmp-pcs-pcie-v6_20.h" #include "phy-qcom-qmp-pcie-qhp.h" /* QPHY_SW_RESET bit */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h new file mode 100644 index 000000000000..e3eb08776339 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ + +/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 + +#endif