| Message ID | 20230215070400.5901-12-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | cb493dad8debeb7eb9537bbeed97743b4c2b8da9 |
| Headers | show |
| Series | arm64: dts: qcom: Supply clock from cpufreq node to CPUs | expand |
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks > to the CPU cores. But this relationship is not represented in DTS so far. > > So let's make cpufreq node as the clock provider and CPU nodes as the > consumers. The clock index for each CPU node is based on the frequency > domain index. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi > index 31b88c738510..58d3b4785401 100644 > --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi > @@ -39,6 +39,7 @@ CPU0: cpu@0 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -58,6 +59,7 @@ CPU1: cpu@100 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_100>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -74,6 +76,7 @@ CPU2: cpu@200 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_200>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -90,6 +93,7 @@ CPU3: cpu@300 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_300>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -106,6 +110,7 @@ CPU4: cpu@400 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x400>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_400>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -122,6 +127,7 @@ CPU5: cpu@500 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x500>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_500>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -139,6 +145,7 @@ CPU6: cpu@600 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x600>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_600>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -155,6 +162,7 @@ CPU7: cpu@700 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x700>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_700>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -1383,6 +1391,7 @@ cpufreq_hw: cpufreq@fd91000 { > <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; > #freq-domain-cells = <1>; > + #clock-cells = <1>; > }; > }; >
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 31b88c738510..58d3b4785401 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -39,6 +39,7 @@ CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -58,6 +59,7 @@ CPU1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -74,6 +76,7 @@ CPU2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -90,6 +93,7 @@ CPU3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -106,6 +110,7 @@ CPU4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -122,6 +127,7 @@ CPU5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -139,6 +145,7 @@ CPU6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -155,6 +162,7 @@ CPU7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -1383,6 +1391,7 @@ cpufreq_hw: cpufreq@fd91000 { <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; };
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)