| Message ID | 20230216125257.112300-10-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs | expand |
On 16.02.2023 13:52, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the high-speed UART port connected to the Bluetooth controller on > the sa8775p-adp development board. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- Same comments as in the previous patch. Konrad > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index 6f96907b335c..1de3b9d4a05a 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -14,6 +14,7 @@ / { > aliases { > serial0 = &uart10; > serial1 = &uart12; > + serial2 = &uart17; > i2c18 = &i2c18; > spi16 = &spi16; > }; > @@ -89,6 +90,29 @@ qup_uart12_tx: qup-uart12-tx-state { > qup_uart12_rx: qup-uart12-rx-state { > pins = "gpio55"; > function = "qup1_se5"; > + }; > + > + qup_uart17_cts: qup-uart17-cts-state { > + pins = "gpio91"; > + function = "qup2_se3"; > + bias-disable; > + }; > + > + qup_uart17_rts: qup0-uart17-rts-state { > + pins = "gpio92"; > + function = "qup2_se3"; > + bias-pull-down; > + }; > + > + qup_uart17_tx: qup0-uart17-tx-state { > + pins = "gpio93"; > + function = "qup2_se3"; > + bias-pull-up; > + }; > + > + qup_uart17_rx: qup0-uart17-rx-state { > + pins = "gpio94"; > + function = "qup2_se3"; > bias-pull-down; > }; > }; > @@ -109,6 +133,15 @@ &uart12 { > status = "okay"; > }; > > +&uart17 { > + pinctrl-0 = <&qup_uart17_cts>, > + <&qup_uart17_rts>, > + <&qup_uart17_tx>, > + <&qup_uart17_rx>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > &xo_board_clk { > clock-frequency = <38400000>; > };
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 6f96907b335c..1de3b9d4a05a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ / { aliases { serial0 = &uart10; serial1 = &uart12; + serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; }; @@ -89,6 +90,29 @@ qup_uart12_tx: qup-uart12-tx-state { qup_uart12_rx: qup-uart12-rx-state { pins = "gpio55"; function = "qup1_se5"; + }; + + qup_uart17_cts: qup-uart17-cts-state { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-state { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-state { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-state { + pins = "gpio94"; + function = "qup2_se3"; bias-pull-down; }; }; @@ -109,6 +133,15 @@ &uart12 { status = "okay"; }; +&uart17 { + pinctrl-0 = <&qup_uart17_cts>, + <&qup_uart17_rts>, + <&qup_uart17_tx>, + <&qup_uart17_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };