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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:15 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:12 +0100 Subject: [PATCH 3/5] drm/msm/a3xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-3-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=1323; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=i47Ky4BsxixFNiVTtrlkGNfUWp9lquZtebebI9yr3wY=; b=v8h6Dm7DVQ7sOt5Zbr5iRrvE0ULoDp8T5pjmqb2KYeBnxk5vKNo9UlQ2/Sso9Qhla9hLMw4Up0kT 4+nWOquwCwmoF65CjP0+7f/xpuDb4iBQzCNUnkIRlGCnRE4TyxfE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for gpu_busy on a3xx, which is required for devfreq support. Signed-off-by: Konrad Dybcio Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) return state; } +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a3xx_gpu_busy, .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space,