| Message ID | 20230222153251.254492-9-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe RC support to Qcom SDX55 SoC | expand |
On 22.02.2023 16:32, Manivannan Sadhasivam wrote: > Enable PCIe RC support on Thundercomm T55 board. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts > index 7ed8feb99afb..fb5b9264077c 100644 > --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts > +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts > @@ -242,6 +242,23 @@ &ipa { > memory-region = <&ipa_fw_mem>; > }; > > +&pcie_phy { > + status = "okay"; 'status' should go last. Since you're introducing new nodes, changing the order in the existing ones would be appreciated. > + > + vdda-phy-supply = <&vreg_l1e_bb_1p2>; > + vdda-pll-supply = <&vreg_l4e_bb_0p875>; > +}; > + > +&pcie_rc { > + status = "okay"; > + > + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_default>; property- property-names Konrad > +}; > + > &qpic_bam { > status = "ok"; > }; > @@ -265,6 +282,31 @@ &remoteproc_mpss { > memory-region = <&mpss_adsp_mem>; > }; > > +&tlmm { > + pcie_default: pcie-default-state { > + clkreq-pins { > + pins = "gpio56"; > + function = "pcie_clkreq"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + perst-pins { > + pins = "gpio57"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + wake-pins { > + pins = "gpio53"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > +}; > + > &usb_hsphy { > status = "okay"; > vdda-pll-supply = <&vreg_l4e_bb_0p875>;
diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afb..fb5b9264077c 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ &ipa { memory-region = <&ipa_fw_mem>; }; +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + +&pcie_rc { + status = "okay"; + + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; +}; + &qpic_bam { status = "ok"; }; @@ -265,6 +282,31 @@ &remoteproc_mpss { memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>;
Enable PCIe RC support on Thundercomm T55 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)