Message ID | 20230306135527.509796-1-abel.vesa@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89 |
Headers | show |
Series | [v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP | expand |
On Mon, 6 Mar 2023 15:55:27 +0200, Abel Vesa wrote: > The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit > LLCC config registers, which means it is writing beyond the upper limit > of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious > impact is the fact that the mentioned slices do not get configured at all, > which will result in reduced performance. Fix that by using the slice ID > values taken from the latest LLCC SC table. > > [...] Applied, thanks! [1/1] soc: qcom: llcc: Fix slice configuration values for SC8280XP commit: 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89 Best regards,
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..26efe12012a0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = { { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, - { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, }; static const struct llcc_slice_config sdm845_data[] = {