| Message ID | 20230308104009.260451-4-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs | expand |
On 8.03.2023 11:40, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add a disabled node for the I2C interface that's exposed on the > sa8775p-ride development board. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 5efb3e4f2335..d65e7826f1d7 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2023, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,icc.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sa8775p-gcc.h> > @@ -502,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 { > clock-names = "m-ahb", "s-ahb"; > iommus = <&apps_smmu 0x5a3 0x0>; > status = "disabled"; > + > + i2c18: i2c@890000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x00890000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; These two should come right before statusdisabled, but I think that's a leftover from 8280 standing out and us having discussions about this and other stuff.. Not sure if we want to untie this knot here on in a big separate commit > + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; interrupts should come after reg > + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + power-domains = <&rpmhpd SA8775P_CX>; > + status = "disabled"; The node contents in general LGTM Konrad > + }; > }; > > intc: interrupt-controller@17a00000 {
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 5efb3e4f2335..d65e7826f1d7 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2023, Linaro Limited */ +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> @@ -502,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 { clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x5a3 0x0>; status = "disabled"; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; intc: interrupt-controller@17a00000 {