| Message ID | 20230313124040.9463-2-quic_kbajaj@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | soc: qcom: llcc: Add support for QDU1000/QRU1000 | expand |
On 23-03-13 18:10:36, Komal Bajaj wrote: > Refactor driver to support multiple configuration for llcc on a target. > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> LGTM. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/soc/qcom/llcc-qcom.c | 191 ++++++++++++++++++++--------------- > 1 file changed, 112 insertions(+), 79 deletions(-) > > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > index 23ce2f78c4ed..00699a0c047e 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -416,92 +416,125 @@ static const u32 llcc_v2_1_reg_offset[] = { > [LLCC_COMMON_STATUS0] = 0x0003400c, > }; > > -static const struct qcom_llcc_config sc7180_cfg = { > - .sct_data = sc7180_data, > - .size = ARRAY_SIZE(sc7180_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sc7180_cfg[] = { > + { > + .sct_data = sc7180_data, > + .size = ARRAY_SIZE(sc7180_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sc7280_cfg = { > - .sct_data = sc7280_data, > - .size = ARRAY_SIZE(sc7280_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sc7280_cfg[] = { > + { > + .sct_data = sc7280_data, > + .size = ARRAY_SIZE(sc7280_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sc8180x_cfg = { > - .sct_data = sc8180x_data, > - .size = ARRAY_SIZE(sc8180x_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sc8180x_cfg[] = { > + { > + .sct_data = sc8180x_data, > + .size = ARRAY_SIZE(sc8180x_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sc8280xp_cfg = { > - .sct_data = sc8280xp_data, > - .size = ARRAY_SIZE(sc8280xp_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sc8280xp_cfg[] = { > + { > + .sct_data = sc8280xp_data, > + .size = ARRAY_SIZE(sc8280xp_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sdm845_cfg = { > - .sct_data = sdm845_data, > - .size = ARRAY_SIZE(sdm845_data), > - .need_llcc_cfg = false, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sdm845_cfg[] = { > + { > + .sct_data = sdm845_data, > + .size = ARRAY_SIZE(sdm845_data), > + .need_llcc_cfg = false, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm6350_cfg = { > - .sct_data = sm6350_data, > - .size = ARRAY_SIZE(sm6350_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sm6350_cfg[] = { > + { > + .sct_data = sm6350_data, > + .size = ARRAY_SIZE(sm6350_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm8150_cfg = { > - .sct_data = sm8150_data, > - .size = ARRAY_SIZE(sm8150_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sm8150_cfg[] = { > + { > + .sct_data = sm8150_data, > + .size = ARRAY_SIZE(sm8150_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm8250_cfg = { > - .sct_data = sm8250_data, > - .size = ARRAY_SIZE(sm8250_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sm8250_cfg[] = { > + { > + .sct_data = sm8250_data, > + .size = ARRAY_SIZE(sm8250_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm8350_cfg = { > - .sct_data = sm8350_data, > - .size = ARRAY_SIZE(sm8350_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v1_reg_offset, > - .edac_reg_offset = &llcc_v1_edac_reg_offset, > +static const struct qcom_llcc_config sm8350_cfg[] = { > + { > + .sct_data = sm8350_data, > + .size = ARRAY_SIZE(sm8350_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_reg_offset, > + .edac_reg_offset = &llcc_v1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm8450_cfg = { > - .sct_data = sm8450_data, > - .size = ARRAY_SIZE(sm8450_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v2_1_reg_offset, > - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, > +static const struct qcom_llcc_config sm8450_cfg[] = { > + { > + .sct_data = sm8450_data, > + .size = ARRAY_SIZE(sm8450_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v2_1_reg_offset, > + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, > + }, > + { }, > }; > > -static const struct qcom_llcc_config sm8550_cfg = { > - .sct_data = sm8550_data, > - .size = ARRAY_SIZE(sm8550_data), > - .need_llcc_cfg = true, > - .reg_offset = llcc_v2_1_reg_offset, > - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, > +static const struct qcom_llcc_config sm8550_cfg[] = { > + { > + .sct_data = sm8550_data, > + .size = ARRAY_SIZE(sm8550_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v2_1_reg_offset, > + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, > + }, > + { }, > }; > > static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; > @@ -966,8 +999,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) > num_banks >>= LLCC_LB_CNT_SHIFT; > drv_data->num_banks = num_banks; > > - llcc_cfg = cfg->sct_data; > - sz = cfg->size; > + llcc_cfg = cfg[0].sct_data; > + sz = cfg[0].size; > > for (i = 0; i < sz; i++) > if (llcc_cfg[i].slice_id > drv_data->max_slices) > @@ -1016,17 +1049,17 @@ static int qcom_llcc_probe(struct platform_device *pdev) > } > > static const struct of_device_id qcom_llcc_of_match[] = { > - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, > - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, > - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, > - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, > - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, > - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, > - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, > - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, > - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, > - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, > - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, > + { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, > + { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, > + { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, > + { .compatible = "qcom,sc8280xp-llcc", .data = sc8280xp_cfg }, > + { .compatible = "qcom,sdm845-llcc", .data = sdm845_cfg }, > + { .compatible = "qcom,sm6350-llcc", .data = sm6350_cfg }, > + { .compatible = "qcom,sm8150-llcc", .data = sm8150_cfg }, > + { .compatible = "qcom,sm8250-llcc", .data = sm8250_cfg }, > + { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, > + { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, > + { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, > { } > }; > MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); > -- > 2.39.1 >
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..00699a0c047e 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -416,92 +416,125 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; -static const struct qcom_llcc_config sc7180_cfg = { - .sct_data = sc7180_data, - .size = ARRAY_SIZE(sc7180_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7180_cfg[] = { + { + .sct_data = sc7180_data, + .size = ARRAY_SIZE(sc7180_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc7280_cfg = { - .sct_data = sc7280_data, - .size = ARRAY_SIZE(sc7280_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7280_cfg[] = { + { + .sct_data = sc7280_data, + .size = ARRAY_SIZE(sc7280_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8180x_cfg = { - .sct_data = sc8180x_data, - .size = ARRAY_SIZE(sc8180x_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8180x_cfg[] = { + { + .sct_data = sc8180x_data, + .size = ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8280xp_cfg = { - .sct_data = sc8280xp_data, - .size = ARRAY_SIZE(sc8280xp_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8280xp_cfg[] = { + { + .sct_data = sc8280xp_data, + .size = ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sdm845_cfg = { - .sct_data = sdm845_data, - .size = ARRAY_SIZE(sdm845_data), - .need_llcc_cfg = false, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sdm845_cfg[] = { + { + .sct_data = sdm845_data, + .size = ARRAY_SIZE(sdm845_data), + .need_llcc_cfg = false, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm6350_cfg = { - .sct_data = sm6350_data, - .size = ARRAY_SIZE(sm6350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm6350_cfg[] = { + { + .sct_data = sm6350_data, + .size = ARRAY_SIZE(sm6350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8150_cfg = { - .sct_data = sm8150_data, - .size = ARRAY_SIZE(sm8150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8150_cfg[] = { + { + .sct_data = sm8150_data, + .size = ARRAY_SIZE(sm8150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8250_cfg = { - .sct_data = sm8250_data, - .size = ARRAY_SIZE(sm8250_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8250_cfg[] = { + { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8350_cfg = { - .sct_data = sm8350_data, - .size = ARRAY_SIZE(sm8350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8350_cfg[] = { + { + .sct_data = sm8350_data, + .size = ARRAY_SIZE(sm8350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8450_cfg = { - .sct_data = sm8450_data, - .size = ARRAY_SIZE(sm8450_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8450_cfg[] = { + { + .sct_data = sm8450_data, + .size = ARRAY_SIZE(sm8450_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8550_cfg = { - .sct_data = sm8550_data, - .size = ARRAY_SIZE(sm8550_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8550_cfg[] = { + { + .sct_data = sm8550_data, + .size = ARRAY_SIZE(sm8550_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -966,8 +999,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; - sz = cfg->size; + llcc_cfg = cfg[0].sct_data; + sz = cfg[0].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) @@ -1016,17 +1049,17 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, + { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, + { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, + { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, + { .compatible = "qcom,sc8280xp-llcc", .data = sc8280xp_cfg }, + { .compatible = "qcom,sdm845-llcc", .data = sdm845_cfg }, + { .compatible = "qcom,sm6350-llcc", .data = sm6350_cfg }, + { .compatible = "qcom,sm8150-llcc", .data = sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = sm8250_cfg }, + { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, + { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, + { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
Refactor driver to support multiple configuration for llcc on a target. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> --- drivers/soc/qcom/llcc-qcom.c | 191 ++++++++++++++++++++--------------- 1 file changed, 112 insertions(+), 79 deletions(-)