@@ -621,6 +621,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
/* ensure no writes happen before the uCode is fully written */
wmb();
+ a6xx_rpmh_stop(gmu);
+
err:
if (!IS_ERR_OR_NULL(pdcptr))
iounmap(pdcptr);
@@ -753,7 +755,6 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
{
- static bool rpmh_init;
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
int ret;
@@ -776,15 +777,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
/* Turn on register retention */
gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
- /* We only need to load the RPMh microcode once */
- if (!rpmh_init) {
- a6xx_gmu_rpmh_init(gmu);
- rpmh_init = true;
- } else {
- ret = a6xx_rpmh_start(gmu);
- if (ret)
- return ret;
- }
+ ret = a6xx_rpmh_start(gmu);
+ if (ret)
+ return ret;
ret = a6xx_gmu_fw_load(gmu);
if (ret)
@@ -1633,6 +1628,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
/* Set up the HFI queues */
a6xx_hfi_init(gmu);
+ /* Initialize RPMh */
+ a6xx_gmu_rpmh_init(gmu);
+
gmu->initialized = true;
return 0;