From patchwork Fri May 5 21:23:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13233082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60923C7EE2C for ; Fri, 5 May 2023 21:24:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232986AbjEEVYP (ORCPT ); Fri, 5 May 2023 17:24:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231438AbjEEVYN (ORCPT ); Fri, 5 May 2023 17:24:13 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BF35E79; Fri, 5 May 2023 14:24:11 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 345JIbGY004308; Fri, 5 May 2023 21:24:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=vXy9duDC4lQn3/CsLZygcxrKTsAek/ssscdyNKOs8TQ=; b=faa1UqfOj2gLxNG9nZAFkCod6DFKTIumtwGO/U+EcgIk2QHf71TyDsF229WURdFGCw3n s6XFpwZF+xrIHADf69VBomlT/gR5O5/Atgzg956Ut9G7Bn1eLKy7gCVKoCdKQDcHXOG7 q8Xo/WKzwI10WzH92oPiOzWaXejHDdff0fErgII2vCv4n2g6AKbu7YJUhcIBWp+4xwKb tLdFCEy3jIPDaZNVgySiP4fOvoLHyzrS6II7VO7Zp7z/+GmRUGYUCREAdSqE14nqX1Hj rAqEU2RGjBwXyT0Oza2KhXDaycZd4faig29dyZ7X3hPu7dXIkzf9+Iuo9IY4ZU3LQZ7C SA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qd3hrgw28-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 May 2023 21:24:05 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 345LO4rF004039 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 May 2023 21:24:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 5 May 2023 14:24:04 -0700 From: Jessica Zhang Date: Fri, 5 May 2023 14:23:51 -0700 Subject: [PATCH v2 4/4] drm/msm/dpu: Set DATA_COMPRESS for command mode MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v2-4-1072c70e9786@quicinc.com> References: <20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683321843; l=3559; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=vZ0+nr8GsTvgyaVtKJinHmx8lZ993+nHYQvEIt3ZMZw=; b=qUvfjdd9piyTkhkZ+1dVBjR7Go0yTUoGHl6QhZ+yg/3euF+yon4WS5ae5w8xKMahHXi7OCQ0p sgfI0VGuEKgA21l6IOERmFykgCpZ8giQ5YU9JZAY474CU+XqYXcehEh X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fTPiaEwA531_rjRP5u4QTY7Gq9T5RAOw X-Proofpoint-GUID: fTPiaEwA531_rjRP5u4QTY7Gq9T5RAOw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-05_27,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305050173 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a DPU INTF op to set DATA_COMPRESS register for command mode panels if the DPU_INTF_DATA_COMPRESS feature flag is set. This flag needs to be enabled in order for DSC v1.2 to work. Note: These changes are for command mode only. Video mode changes will be posted along with the DSC v1.2 support for DP. Changes in v2: - Fixed whitespace issue in macro definition - Read INTF_CONFIG2 before writing to DATA_COMPRESS bit - Only set dpu_hw_intf_ops.data_compress if DATA_COMPRESS feature is set - Removed `inline` from dpu_hw_intf_enable_compression declaration Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index d8ed85a238af..1a4c20f02312 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -68,6 +68,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( phys_enc->hw_intf, true, phys_enc->hw_pp->idx); + + if (phys_enc->hw_intf->ops.enable_compression) + phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf); } static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 6485500eedb8..322c55a5042c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -91,6 +91,14 @@ #define INTF_CFG2_DATABUS_WIDEN BIT(0) #define INTF_CFG2_DATA_HCTL_EN BIT(4) +#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) + +static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx) +{ + u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); + + DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2 | INTF_CFG2_DCE_DATA_COMPRESS); +} static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, const struct intf_timing_params *p, @@ -542,6 +550,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->vsync_sel = dpu_hw_intf_vsync_sel; ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh; } + + if (cap & BIT(DPU_INTF_DATA_COMPRESS)) + ops->enable_compression = dpu_hw_intf_enable_compression; } struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 73b0885918f8..a8def68a5ec2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -70,6 +70,7 @@ struct intf_status { * @get_autorefresh: Retrieve autorefresh config from hardware * Return: 0 on success, -ETIMEDOUT on timeout * @vsync_sel: Select vsync signal for tear-effect configuration + * @enable_compression: Enable data compression */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, @@ -107,6 +108,7 @@ struct dpu_hw_intf_ops { * Disable autorefresh if enabled */ void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay); + void (*enable_compression)(struct dpu_hw_intf *intf); }; struct dpu_hw_intf {