| Message ID | 20230501143445.3851-8-quic_kriskura@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
On 01/05/2023 16:34, Krishna Kurapati wrote: > Add USB and DWC3 node for tertiary port of SC8280 along with multiport > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > platforms. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 8fa9fbfe5d00..0e4fb286956b 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint { > }; > }; > > + usb_2: usb@a4f8800 { Nodes are ordered by unit address, more or less. > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; > + reg = <0 0x0a4f8800 0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_SLEEP_CLK>, > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; > + > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; Does not look aligned. > + > + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", > + "ss_phy_irq", "pwr_event_1", Does not look aligned. > + "pwr_event_2", "pwr_event_3", > + "pwr_event_4"; > + > + power-domains = <&gcc USB30_MP_GDSC>; > + > + resets = <&gcc GCC_USB30_MP_BCR>; > + > + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > + required-opps = <&rpmhpd_opp_nom>; > + Please open the DTSI and look how this is organized there. I don't think doing this differently - with different order - helps to review. required-opps is next to power-domains. > + status = "disabled"; > + > + usb_2_dwc3: usb@a400000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a400000 0 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x800 0x0>; > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, > + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, > + <&usb_2_hsphy2>, > + <&usb_2_hsphy3>; > + phy-names = "usb2-port0", "usb3-port0", > + "usb2-port1", "usb3-port1", > + "usb2-port2", > + "usb2-port3"; > + }; > + }; > + > mdss0: display-subsystem@ae00000 { > compatible = "qcom,sc8280xp-mdss"; > reg = <0 0x0ae00000 0 0x1000>; Best regards, Krzysztof
On 5/2/2023 1:17 PM, Krzysztof Kozlowski wrote: > On 01/05/2023 16:34, Krishna Kurapati wrote: >> Add USB and DWC3 node for tertiary port of SC8280 along with multiport >> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride >> platforms. >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> index 8fa9fbfe5d00..0e4fb286956b 100644 >> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint { >> }; >> }; >> >> + usb_2: usb@a4f8800 { > > Nodes are ordered by unit address, more or less > >> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; >> + reg = <0 0x0a4f8800 0 0x400>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, >> + <&gcc GCC_USB30_MP_MASTER_CLK>, >> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, >> + <&gcc GCC_USB30_MP_SLEEP_CLK>, >> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, >> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; >> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", >> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; >> + >> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_MP_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <200000000>; >> + >> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 126 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; > > Does not look aligned. > >> + >> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", >> + "ss_phy_irq", "pwr_event_1", > > Does not look aligned. > Sure, will fix up the indentation issues. >> + "pwr_event_2", "pwr_event_3", >> + "pwr_event_4"; >> + >> + power-domains = <&gcc USB30_MP_GDSC>; >> + >> + resets = <&gcc GCC_USB30_MP_BCR>; >> + >> + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; >> + interconnect-names = "usb-ddr", "apps-usb"; >> + >> + required-opps = <&rpmhpd_opp_nom>; >> + > > Please open the DTSI and look how this is organized there. I don't think > doing this differently - with different order - helps to review. > required-opps is next to power-domains. Sure. Will fix it up. > >> + status = "disabled"; >> + >> + usb_2_dwc3: usb@a400000 { >> + compatible = "snps,dwc3"; >> + reg = <0 0x0a400000 0 0xcd00>; >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + iommus = <&apps_smmu 0x800 0x0>; >> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, >> + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, >> + <&usb_2_hsphy2>, >> + <&usb_2_hsphy3>; >> + phy-names = "usb2-port0", "usb3-port0", >> + "usb2-port1", "usb3-port1", >> + "usb2-port2", >> + "usb2-port3"; >> + }; >> + }; >> + >> mdss0: display-subsystem@ae00000 { >> compatible = "qcom,sc8280xp-mdss"; >> reg = <0 0x0ae00000 0 0x1000>; > Thanks, Krishna,
On Mon, May 01, 2023 at 08:04:43PM +0530, Krishna Kurapati wrote: > Add USB and DWC3 node for tertiary port of SC8280 along with multiport > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > platforms. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 8fa9fbfe5d00..0e4fb286956b 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint { > }; > }; > > + usb_2: usb@a4f8800 { > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; > + reg = <0 0x0a4f8800 0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_SLEEP_CLK>, > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; > + > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; This looks wrong. You're missing the &intc phandle for the last four entries: DTC arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dtb /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/display-subsystem@ae00000/displayport-controller@aea0000/opp-table or bad phandle (referred from interrupts-extended[10]) also defined at /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sa8540p-ride.dts:312.8-317.3 /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/display-subsystem@ae00000/displayport-controller@ae9a000/ports/port@0/endpoint or bad phandle (referred from interrupts-extended[10]) also defined at /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sa8295p-adp.dts:587.8-594.3 /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /interconnect-mmss-noc or bad phandle (referred from interrupts-extended[10]) /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/phy@88e7000 or bad phandle (referred from interrupts-extended[10]) > + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", > + "ss_phy_irq", "pwr_event_1", > + "pwr_event_2", "pwr_event_3", > + "pwr_event_4"; Also the order does not match the binding where you had the pwr_event interrupts first. Johan
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 8fa9fbfe5d00..0e4fb286956b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint { }; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", + "ss_phy_irq", "pwr_event_1", + "pwr_event_2", "pwr_event_3", + "pwr_event_4"; + + power-domains = <&gcc USB30_MP_GDSC>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + required-opps = <&rpmhpd_opp_nom>; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-port0", "usb3-port0", + "usb2-port1", "usb3-port1", + "usb2-port2", + "usb2-port3"; + }; + }; + mdss0: display-subsystem@ae00000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x0ae00000 0 0x1000>;
Add USB and DWC3 node for tertiary port of SC8280 along with multiport IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride platforms. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)