| Message ID | 20230518113800.339158-6-srinivas.kandagatla@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: sc8280xp: add lpasscc reset control | expand |
On Thu, May 18, 2023 at 12:38:00PM +0100, Srinivas Kandagatla wrote: > Soundwire controllers on sc8280xp needs an explicit reset, this > patch adds support for this. s/this patch adds/add/ > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index d2a2224d138a..a2d0f8abe23d 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> > +#include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interconnect/qcom,osm-l3.h> > #include <dt-bindings/interconnect/qcom,sc8280xp.h> > @@ -2548,6 +2549,8 @@ rxmacro: rxmacro@3200000 { > swr1: soundwire-controller@3210000 { > compatible = "qcom,soundwire-v1.6.0"; > reg = <0 0x03210000 0 0x2000>; > + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; > + reset-names = "swr_audio_cgcr"; Move after clocks. > interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&rxmacro>; > clock-names = "iface"; > @@ -2647,6 +2650,13 @@ swr0: soundwire-controller@3250000 { > status = "disabled"; > }; > > + lpass_audiocc: clock-controller@3300000 { > + compatible = "qcom,sc8280xp-lpassaudiocc"; > + reg = <0 0x032a9000 0 0x1000>; Either this property or the unit address is wrong as they do not match. The bindings currently mandates that vendor property you added ("qcom,adsp-pil-mode), but you left it out here. > + #reset-cells = <1>; > + #clock-cells = <1>; clock before reset for some sort order. > + }; > + Your preliminary version of this patch also added a reset to swr0, which has been left out here. Was that not needed? > swr2: soundwire-controller@3330000 { > compatible = "qcom,soundwire-v1.6.0"; > reg = <0 0x03330000 0 0x2000>; > @@ -2654,6 +2664,8 @@ swr2: soundwire-controller@3330000 { > <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "core", "wakeup"; > > + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; > + reset-names = "swr_audio_cgcr"; Add after clocks. > clocks = <&txmacro>; > clock-names = "iface"; > label = "TX"; > @@ -2849,6 +2861,13 @@ data-pins { > }; > }; > > + lpasscc: clock-controller@33e0000 { > + compatible = "qcom,sc8280xp-lpasscc"; > + reg = <0 0x033e0000 0 0x21000>; Your driver (and the binding example) seems to suggest that the size here should be 0x12000. The vendor property appears to be missing here too (or the binding is incorrect). > + #reset-cells = <1>; > + #clock-cells = <1>; clock before reset > + }; > + > usb_0_qmpphy: phy@88eb000 { > compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; > reg = <0 0x088eb000 0 0x4000>; Johan
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d2a2224d138a..a2d0f8abe23d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> +#include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> @@ -2548,6 +2549,8 @@ rxmacro: rxmacro@3200000 { swr1: soundwire-controller@3210000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03210000 0 0x2000>; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rxmacro>; clock-names = "iface"; @@ -2647,6 +2650,13 @@ swr0: soundwire-controller@3250000 { status = "disabled"; }; + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x032a9000 0 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + }; + swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; @@ -2654,6 +2664,8 @@ swr2: soundwire-controller@3330000 { <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core", "wakeup"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; clocks = <&txmacro>; clock-names = "iface"; label = "TX"; @@ -2849,6 +2861,13 @@ data-pins { }; }; + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0 0x033e0000 0 0x21000>; + #reset-cells = <1>; + #clock-cells = <1>; + }; + usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088eb000 0 0x4000>;
Soundwire controllers on sc8280xp needs an explicit reset, this patch adds support for this. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)