| Message ID | 20230527093934.101335-4-y.oudjana@protonmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | MSM8996 Pro CBF scaling support | expand |
On 27.05.2023 11:39, Yassine Oudjana wrote: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the > difference accordingly. > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > drivers/clk/qcom/clk-cbf-8996.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c > index cfd567636f4e..ab988e6f1976 100644 > --- a/drivers/clk/qcom/clk-cbf-8996.c > +++ b/drivers/clk/qcom/clk-cbf-8996.c > @@ -48,7 +48,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { > [PLL_OFF_STATUS] = 0x28, > }; > > -static const struct alpha_pll_config cbfpll_config = { > +static struct alpha_pll_config cbfpll_config = { > .l = 72, > .config_ctl_val = 0x200d4828, > .config_ctl_hi_val = 0x006, > @@ -137,7 +137,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, > { > struct clk_hw *parent; > > - if (req->rate < (DIV_THRESHOLD / 2)) > + if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) > return -EINVAL; > > if (req->rate < DIV_THRESHOLD) > @@ -265,6 +265,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) > /* Switch CBF to use the primary PLL */ > regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); > > + if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) { If this was a driver for more than 1.5 SoCs, I'd propose using a different mechanism here (match data flags or something), but since there aren't (and hopefully won't ever be) more 8996s (automotive etc. inherit one of these configurations so that doesn't count), I'm willing to say Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + cbfpll_config.post_div_val = 0x3 << 8; > + cbf_pll_postdiv.div = 4; > + } > + > for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) { > ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]); > if (ret) > @@ -286,6 +291,7 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) > > static const struct of_device_id qcom_msm8996_cbf_match_table[] = { > { .compatible = "qcom,msm8996-cbf" }, > + { .compatible = "qcom,msm8996pro-cbf" }, > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);
On 29/05/2023 11:18, Konrad Dybcio wrote: > > > On 27.05.2023 11:39, Yassine Oudjana wrote: >> From: Yassine Oudjana <y.oudjana@protonmail.com> >> >> The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the >> difference accordingly. >> >> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> >> --- >> drivers/clk/qcom/clk-cbf-8996.c | 10 ++++++++-- >> 1 file changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c >> index cfd567636f4e..ab988e6f1976 100644 >> --- a/drivers/clk/qcom/clk-cbf-8996.c >> +++ b/drivers/clk/qcom/clk-cbf-8996.c >> @@ -48,7 +48,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { >> [PLL_OFF_STATUS] = 0x28, >> }; >> >> -static const struct alpha_pll_config cbfpll_config = { >> +static struct alpha_pll_config cbfpll_config = { >> .l = 72, >> .config_ctl_val = 0x200d4828, >> .config_ctl_hi_val = 0x006, >> @@ -137,7 +137,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, >> { >> struct clk_hw *parent; >> >> - if (req->rate < (DIV_THRESHOLD / 2)) >> + if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) >> return -EINVAL; >> >> if (req->rate < DIV_THRESHOLD) >> @@ -265,6 +265,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) >> /* Switch CBF to use the primary PLL */ >> regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); >> >> + if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) { > If this was a driver for more than 1.5 SoCs, I'd propose using a > different mechanism here (match data flags or something), but since > there aren't (and hopefully won't ever be) more 8996s (automotive etc. > inherit one of these configurations so that doesn't count), I'm willing > to say Fingers crossed for no additional 8996 variants. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c index cfd567636f4e..ab988e6f1976 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -48,7 +48,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_STATUS] = 0x28, }; -static const struct alpha_pll_config cbfpll_config = { +static struct alpha_pll_config cbfpll_config = { .l = 72, .config_ctl_val = 0x200d4828, .config_ctl_hi_val = 0x006, @@ -137,7 +137,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, { struct clk_hw *parent; - if (req->rate < (DIV_THRESHOLD / 2)) + if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) return -EINVAL; if (req->rate < DIV_THRESHOLD) @@ -265,6 +265,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) /* Switch CBF to use the primary PLL */ regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); + if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) { + cbfpll_config.post_div_val = 0x3 << 8; + cbf_pll_postdiv.div = 4; + } + for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) { ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]); if (ret) @@ -286,6 +291,7 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) static const struct of_device_id qcom_msm8996_cbf_match_table[] = { { .compatible = "qcom,msm8996-cbf" }, + { .compatible = "qcom,msm8996pro-cbf" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);