From patchwork Mon Jun 5 18:44:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Thierry X-Patchwork-Id: 13267880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD980C7EE23 for ; Mon, 5 Jun 2023 18:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234863AbjFESqO (ORCPT ); Mon, 5 Jun 2023 14:46:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234557AbjFESqO (ORCPT ); Mon, 5 Jun 2023 14:46:14 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8BACF1 for ; Mon, 5 Jun 2023 11:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1685990723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cIk38l37E6hXe6+p5eeVC3Bjfx5cAZMiuspPWHWk1HU=; b=a2bhd45PnqXFKbm4RgHTfH7gbZMC2Bkn+6C9aVD7iTcLbCGtTys4xuHh1dwS+tABzRj8BB V8Q4TWPO6QbbG0504VQdqhofRT9JC+O9eIw3qPO3pxqoqoB/F9VZhmDOK9nieUKclFec40 NsuqCIbe+9E4cU1/Q3lMdG0jqq7wvfc= Received: from mail-oi1-f200.google.com (mail-oi1-f200.google.com [209.85.167.200]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-117-EEI90alZNAaPz4Dn0L7Kyw-1; Mon, 05 Jun 2023 14:45:22 -0400 X-MC-Unique: EEI90alZNAaPz4Dn0L7Kyw-1 Received: by mail-oi1-f200.google.com with SMTP id 5614622812f47-38bedafc58dso3885825b6e.0 for ; Mon, 05 Jun 2023 11:45:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685990722; x=1688582722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cIk38l37E6hXe6+p5eeVC3Bjfx5cAZMiuspPWHWk1HU=; b=j/I0K6MelWDuJzRMcrhn1tyrcCSnU+AWUgj87lihkKLFZ/bcR2Qh+LY641T5v1AaFX etPTs9qNWk2xdcClz93YP6CNcksxYZ7iof95AiDe7qi0HRqPOCukr1mr5wlqmvwC5f2I ZR42ClaUPSYBLkg2gFmEdP2T833wFIc6Ci5jRpseKESQKCkPostwPLxInBMH2YxjbnzT 1Xvh8SpaoxSVh3ZhDaKEO9OS85QBIK9rpzAWjzLaybmFQous+HvwuuCIYRcfRAVlIqUB wNr1N+LDV/PtIpp1S/3IAT69js3RAnCREOOI0uI1mFHtnQSctLfcciCWXKhhpYnCLXVA vbAA== X-Gm-Message-State: AC+VfDwkW7zTixgEL9jJWdlj96ruKNhgQBTZY02LcA1QmupwKvBvgMrm rS4nqqsYDQ5tBYuf+8H3x99OxQHa09cotMwv5PQMHXA8dzoSFPp7j5+hNn3C2BYr/a5J99o0zrv 6HuD6/Tp6GLOc/wRSDHI22Ecc0EHxF//NiA== X-Received: by 2002:aca:d0e:0:b0:39a:be43:6f13 with SMTP id 14-20020aca0d0e000000b0039abe436f13mr2661001oin.43.1685990721877; Mon, 05 Jun 2023 11:45:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5aKRoOVG33caBXHFKr+14vig9tpTuBnhpRF8RLbpsx2FRYHffkPb3HLCIfmdsedIIYhKcWXg== X-Received: by 2002:aca:d0e:0:b0:39a:be43:6f13 with SMTP id 14-20020aca0d0e000000b0039abe436f13mr2660983oin.43.1685990721608; Mon, 05 Jun 2023 11:45:21 -0700 (PDT) Received: from fedora.redhat.com ([107.171.218.122]) by smtp.gmail.com with ESMTPSA id d10-20020a0cc68a000000b00625da789003sm4785771qvj.110.2023.06.05.11.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 11:45:21 -0700 (PDT) From: Adrien Thierry To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Stephen Boyd , Manu Gautam , Wesley Cheng , Philipp Zabel Cc: Adrien Thierry , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 1/2] phy: qcom-snps-femto-v2: properly enable ref clock Date: Mon, 5 Jun 2023 14:44:53 -0400 Message-Id: <20230605184455.34832-2-athierry@redhat.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605184455.34832-1-athierry@redhat.com> References: <20230605184455.34832-1-athierry@redhat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The driver is not enabling the ref clock, which thus gets disabled by the clk_disable_unused initcall. This leads to the dwc3 controller failing to initialize if probed after clk_disable_unused is called, for instance when the driver is built as a module. To fix this, switch to the clk_bulk API to handle both cfg_ahb and ref clocks at the proper places. Note that the cfg_ahb clock is currently not used by any device tree instantiation of the PHY. Work needs to be done separately to fix this. Link: https://lore.kernel.org/linux-arm-msm/ZEqvy+khHeTkC2hf@fedora/ Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Adrien Thierry Reviewed-by: Andrew Halaney --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 67 ++++++++++++++----- 1 file changed, 49 insertions(+), 18 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 6c237f3cc66d..ce1d2f8b568a 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -110,11 +110,13 @@ struct phy_override_seq { /** * struct qcom_snps_hsphy - snps hs phy attributes * + * @dev: device structure + * * @phy: generic phy * @base: iomapped memory space for snps hs phy * - * @cfg_ahb_clk: AHB2PHY interface clock - * @ref_clk: phy reference clock + * @num_clks: number of clocks + * @clks: array of clocks * @phy_reset: phy reset control * @vregs: regulator supplies bulk data * @phy_initialized: if PHY has been initialized correctly @@ -122,11 +124,13 @@ struct phy_override_seq { * @update_seq_cfg: tuning parameters for phy init */ struct qcom_snps_hsphy { + struct device *dev; + struct phy *phy; void __iomem *base; - struct clk *cfg_ahb_clk; - struct clk *ref_clk; + int num_clks; + struct clk_bulk_data *clks; struct reset_control *phy_reset; struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; @@ -135,6 +139,32 @@ struct qcom_snps_hsphy { struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; }; +static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy) +{ + struct device *dev = hsphy->dev; + + hsphy->num_clks = 2; + hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); + if (!hsphy->clks) + return -ENOMEM; + + /* + * HACK: For cfg_ahb clock, use devm_clk_get_optional() because currently no device + * tree instantiation of the PHY is using the clock. This needs to be fixed in order + * for this code to be able to use devm_clk_bulk_get(). + */ + hsphy->clks[0].id = "cfg_ahb"; + hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); + + hsphy->clks[1].id = "ref"; + hsphy->clks[1].clk = devm_clk_get(dev, "ref"); + if (IS_ERR(hsphy->clks[1].clk)) + return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk), + "failed to get ref clk\n"); + + return 0; +} + static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, u32 mask, u32 val) { @@ -165,7 +195,7 @@ static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy) 0, USB2_AUTO_RESUME); } - clk_disable_unprepare(hsphy->cfg_ahb_clk); + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); return 0; } @@ -175,9 +205,9 @@ static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy) dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n"); - ret = clk_prepare_enable(hsphy->cfg_ahb_clk); + ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); if (ret) { - dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n"); + dev_err(&hsphy->phy->dev, "failed to enable clocks\n"); return ret; } @@ -374,16 +404,16 @@ static int qcom_snps_hsphy_init(struct phy *phy) if (ret) return ret; - ret = clk_prepare_enable(hsphy->cfg_ahb_clk); + ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); if (ret) { - dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); + dev_err(&phy->dev, "failed to enable clocks, %d\n", ret); goto poweroff_phy; } ret = reset_control_assert(hsphy->phy_reset); if (ret) { dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); - goto disable_ahb_clk; + goto disable_clks; } usleep_range(100, 150); @@ -391,7 +421,7 @@ static int qcom_snps_hsphy_init(struct phy *phy) ret = reset_control_deassert(hsphy->phy_reset); if (ret) { dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); - goto disable_ahb_clk; + goto disable_clks; } qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, @@ -448,8 +478,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) return 0; -disable_ahb_clk: - clk_disable_unprepare(hsphy->cfg_ahb_clk); +disable_clks: + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); poweroff_phy: regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); @@ -461,7 +491,7 @@ static int qcom_snps_hsphy_exit(struct phy *phy) struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); reset_control_assert(hsphy->phy_reset); - clk_disable_unprepare(hsphy->cfg_ahb_clk); + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); hsphy->phy_initialized = false; @@ -554,14 +584,15 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) if (!hsphy) return -ENOMEM; + hsphy->dev = dev; + hsphy->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hsphy->base)) return PTR_ERR(hsphy->base); - hsphy->ref_clk = devm_clk_get(dev, "ref"); - if (IS_ERR(hsphy->ref_clk)) - return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk), - "failed to get ref clk\n"); + ret = qcom_snps_hsphy_clk_init(hsphy); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize clocks\n"); hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(hsphy->phy_reset)) {