From patchwork Wed Jun 21 15:27:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13287502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D2FEEB64DC for ; Wed, 21 Jun 2023 15:27:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbjFUP13 (ORCPT ); Wed, 21 Jun 2023 11:27:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232094AbjFUP11 (ORCPT ); Wed, 21 Jun 2023 11:27:27 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48785A1 for ; Wed, 21 Jun 2023 08:27:26 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2b475b54253so56180531fa.2 for ; Wed, 21 Jun 2023 08:27:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687361244; x=1689953244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MicCFkNBouLiXbSIH4JKKed61jEBtgAzBmipuLWTl/4=; b=OwG0hwW0S7dRHg5+B6A1m+O34iprVP9IxKbiSOa842rI7m8tfyPUQWw6h09X0boARt NPaCs3pEn49L8ND221/Q8GbCAych5gOKHun8P4OlzyNqgnwnflwv0obcStqFwIsPufeE J6F6NGhmoQ9ns11x4ItHR2Ld+O6HC+xRsAjNanx9ATC0wYFl6RcFSs9WxWI21DUoyzbq tE2DKuqsnR0hODvSEiN6cZNd4VMjr9kAU8LSUhryYyrZCi1/eIXk304/YT9sQNhO99Cs Oh4eYoaEsoNZdFWaZNnrzSUO+1szmlEjFtiJErMfV+pnNkNopj7eJ18gQ2Yv5xS9eqyd MtaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687361244; x=1689953244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MicCFkNBouLiXbSIH4JKKed61jEBtgAzBmipuLWTl/4=; b=A7aINdVABdEdh7ltchYYvd5mkwHsciMjVGoiE6xdcJgvPhlwD7UseJAUNKkB38LxkW Ejm5xp68r6vU3nwwWGAze51vjadlwKZFBH17XgT4AyIb0NR8fTukgRmKOesSG6uwIo2i ezMBoapCw/9Mrlid3uRz5sf1A5bi4JJV6ls3sIew5Qqb6IGUAqrsW853AHZ6GOufvn5z jhfABBBAhZiCI/995AyD9sVGgfKb9L26wVL/kgVcXjT0LgcGadvGJWCg6Ffba5dJz5L2 w3WVbGLVAFK2cIp3FwsaVMjcNFBTFxDsATxEMfqfUDVqfcKDp1PaqsyGZ/6cpxKoicIi U7Sw== X-Gm-Message-State: AC+VfDwUG8uqcyn5KkygWpxyfl+1PwiYcSJVRsexJ3MUVKAMBILagIAP Kfrxk4hvvtH+n93zk0ymAgwfUQ== X-Google-Smtp-Source: ACHHUZ47h1YAEkKvaIBd+vlDcOPUhPGiWaVilv8f4vYR2MfIO2CWbO/0vX0NLssZ8eZYZuRYqMk1xw== X-Received: by 2002:a2e:740e:0:b0:2b5:86e4:558e with SMTP id p14-20020a2e740e000000b002b586e4558emr1360325ljc.38.1687361244414; Wed, 21 Jun 2023 08:27:24 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id o11-20020a2e9b4b000000b002ad5f774579sm926408ljj.96.2023.06.21.08.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 08:27:23 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Michael Turquette Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong Subject: [PATCH 4/7] phy: qcom: qmp-combo: reuse register layouts for some more registers Date: Wed, 21 Jun 2023 18:27:16 +0300 Message-Id: <20230621152719.1025801-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230621152719.1025801-1-dmitry.baryshkov@linaro.org> References: <20230621152719.1025801-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 34 ++++++++++++------- .../qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 2 ++ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 2f95e29110df..d034b4f45bd3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -116,6 +116,8 @@ enum qphy_reg_layout { QPHY_TX_TX_POL_INV, QPHY_TX_TX_DRV_LVL, QPHY_TX_TX_EMP_POST1_LVL, + QPHY_TX_HIGHZ_DRVR_EN, + QPHY_TX_TRANSCEIVER_BIAS_EN, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE @@ -138,6 +140,8 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, }; static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -159,6 +163,8 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, }; static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -180,6 +186,8 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, }; static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -201,6 +209,8 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, }; static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { @@ -2346,10 +2356,10 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) drvr1_en = 0x10; } - writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(2000); @@ -2406,10 +2416,10 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) drvr1_en = 0x10; } - writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); - writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); - writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(2000); @@ -2464,10 +2474,10 @@ static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp) drvr1_en = 0x10; } - writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(2000); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h index b4810c48dc20..8883e1de730e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h @@ -17,6 +17,8 @@ #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 +#define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 #define QSERDES_V6_TX_TX_POL_INV 0x5c #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 #define QSERDES_V6_TX_BIST_PATTERN7 0x7c