| Message ID | 20230624-sm6125-dpu-v1-11-1d5a638cebf2@somainline.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm: Add SM6125 MDSS/DPU hardware and enable Sony Xperia 10 II panel | expand |
On 24.06.2023 02:41, Marijn Suijten wrote: > SM6125 features only a single PHY (despite a secondary PHY PLL source > being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream > sources for this "trinket" SoC do not define the typical "vcca" > regulator to be available nor used. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- The introduced ops are identical to 2290, modulo regulator.. But the regulator is absent on both (VDD_MX powers it instead), so feel free to clean that up and reuse it ;) Konrad > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ > 3 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 9d5795c58a98..8688ed502dcf 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_14nm_2290_cfgs }, > { .compatible = "qcom,dsi-phy-14nm-660", > .data = &dsi_phy_14nm_660_cfgs }, > + { .compatible = "qcom,dsi-phy-14nm-6125", > + .data = &dsi_phy_14nm_6125_cfgs }, > { .compatible = "qcom,dsi-phy-14nm-8953", > .data = &dsi_phy_14nm_8953_cfgs }, > #endif > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 8b640d174785..ebf915f5e6c6 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 3ce45b023e63..5d43c9ec69ae 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { > .num_dsi_phy = 2, > }; > > +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { > + .has_phy_lane = true, > + .ops = { > + .enable = dsi_14nm_phy_enable, > + .disable = dsi_14nm_phy_disable, > + .pll_init = dsi_pll_14nm_init, > + .save_pll_state = dsi_14nm_pll_save_state, > + .restore_pll_state = dsi_14nm_pll_restore_state, > + }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > + .io_start = { 0x5e94400 }, > + .num_dsi_phy = 1, > +}; > + > const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { > .has_phy_lane = true, > .regulator_data = dsi_phy_14nm_17mA_regulators, >
On 24/06/2023 04:49, Konrad Dybcio wrote: > On 24.06.2023 02:41, Marijn Suijten wrote: >> SM6125 features only a single PHY (despite a secondary PHY PLL source >> being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream >> sources for this "trinket" SoC do not define the typical "vcca" >> regulator to be available nor used. >> >> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >> --- > The introduced ops are identical to 2290, modulo regulator.. > > But the regulator is absent on both (VDD_MX powers it instead), so > feel free to clean that up and reuse it ;) Could you please send a fix for qcm2290? > > Konrad >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ >> 3 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> index 9d5795c58a98..8688ed502dcf 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { >> .data = &dsi_phy_14nm_2290_cfgs }, >> { .compatible = "qcom,dsi-phy-14nm-660", >> .data = &dsi_phy_14nm_660_cfgs }, >> + { .compatible = "qcom,dsi-phy-14nm-6125", >> + .data = &dsi_phy_14nm_6125_cfgs }, >> { .compatible = "qcom,dsi-phy-14nm-8953", >> .data = &dsi_phy_14nm_8953_cfgs }, >> #endif >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> index 8b640d174785..ebf915f5e6c6 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >> index 3ce45b023e63..5d43c9ec69ae 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >> @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { >> .num_dsi_phy = 2, >> }; >> >> +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { >> + .has_phy_lane = true, >> + .ops = { >> + .enable = dsi_14nm_phy_enable, >> + .disable = dsi_14nm_phy_disable, >> + .pll_init = dsi_pll_14nm_init, >> + .save_pll_state = dsi_14nm_pll_save_state, >> + .restore_pll_state = dsi_14nm_pll_restore_state, >> + }, >> + .min_pll_rate = VCO_MIN_RATE, >> + .max_pll_rate = VCO_MAX_RATE, >> + .io_start = { 0x5e94400 }, >> + .num_dsi_phy = 1, >> +}; >> + >> const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { >> .has_phy_lane = true, >> .regulator_data = dsi_phy_14nm_17mA_regulators, >>
On 2023-06-24 03:49:25, Konrad Dybcio wrote: > On 24.06.2023 02:41, Marijn Suijten wrote: > > SM6125 features only a single PHY (despite a secondary PHY PLL source > > being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream > > sources for this "trinket" SoC do not define the typical "vcca" > > regulator to be available nor used. > > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > The introduced ops are identical to 2290, modulo regulator.. Sure, I can create a "drop unused regulators from 14nm qcm2290 config" and a second "reuse qcm2290 14nm dsi phy for sm6125" patch, instead of this one. > But the regulator is absent on both (VDD_MX powers it instead), so In the DT patch you requested me to use CX instead of MX... Which one is it? Also note that I moved it from DSI PHY to DSI0 because that's where the rpmpd opps reside. - Marijn > feel free to clean that up and reuse it ;) > > Konrad > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ > > 3 files changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > index 9d5795c58a98..8688ed502dcf 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > > .data = &dsi_phy_14nm_2290_cfgs }, > > { .compatible = "qcom,dsi-phy-14nm-660", > > .data = &dsi_phy_14nm_660_cfgs }, > > + { .compatible = "qcom,dsi-phy-14nm-6125", > > + .data = &dsi_phy_14nm_6125_cfgs }, > > { .compatible = "qcom,dsi-phy-14nm-8953", > > .data = &dsi_phy_14nm_8953_cfgs }, > > #endif > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > index 8b640d174785..ebf915f5e6c6 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; > > +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > index 3ce45b023e63..5d43c9ec69ae 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { > > .num_dsi_phy = 2, > > }; > > > > +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { > > + .has_phy_lane = true, > > + .ops = { > > + .enable = dsi_14nm_phy_enable, > > + .disable = dsi_14nm_phy_disable, > > + .pll_init = dsi_pll_14nm_init, > > + .save_pll_state = dsi_14nm_pll_save_state, > > + .restore_pll_state = dsi_14nm_pll_restore_state, > > + }, > > + .min_pll_rate = VCO_MIN_RATE, > > + .max_pll_rate = VCO_MAX_RATE, > > + .io_start = { 0x5e94400 }, > > + .num_dsi_phy = 1, > > +}; > > + > > const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { > > .has_phy_lane = true, > > .regulator_data = dsi_phy_14nm_17mA_regulators, > >
On 25.06.2023 22:23, Marijn Suijten wrote: > On 2023-06-24 03:49:25, Konrad Dybcio wrote: >> On 24.06.2023 02:41, Marijn Suijten wrote: >>> SM6125 features only a single PHY (despite a secondary PHY PLL source >>> being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream >>> sources for this "trinket" SoC do not define the typical "vcca" >>> regulator to be available nor used. >>> >>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>> --- >> The introduced ops are identical to 2290, modulo regulator.. > > Sure, I can create a "drop unused regulators from 14nm qcm2290 config" > and a second "reuse qcm2290 14nm dsi phy for sm6125" patch, instead of > this one. Please do. > >> But the regulator is absent on both (VDD_MX powers it instead), so > > In the DT patch you requested me to use CX instead of MX... Which one is > it? You're confusing DSI host with DSI PHY. > > Also note that I moved it from DSI PHY to DSI0 because that's where the > rpmpd opps reside. Both of them need their separate power lines to be active! Also, OPP is not necessary for genpd activation. Konrad > > - Marijn > >> feel free to clean that up and reuse it ;) > >> >> Konrad >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ >>> 3 files changed, 18 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> index 9d5795c58a98..8688ed502dcf 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { >>> .data = &dsi_phy_14nm_2290_cfgs }, >>> { .compatible = "qcom,dsi-phy-14nm-660", >>> .data = &dsi_phy_14nm_660_cfgs }, >>> + { .compatible = "qcom,dsi-phy-14nm-6125", >>> + .data = &dsi_phy_14nm_6125_cfgs }, >>> { .compatible = "qcom,dsi-phy-14nm-8953", >>> .data = &dsi_phy_14nm_8953_cfgs }, >>> #endif >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> index 8b640d174785..ebf915f5e6c6 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; >>> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >>> index 3ce45b023e63..5d43c9ec69ae 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c >>> @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { >>> .num_dsi_phy = 2, >>> }; >>> >>> +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { >>> + .has_phy_lane = true, >>> + .ops = { >>> + .enable = dsi_14nm_phy_enable, >>> + .disable = dsi_14nm_phy_disable, >>> + .pll_init = dsi_pll_14nm_init, >>> + .save_pll_state = dsi_14nm_pll_save_state, >>> + .restore_pll_state = dsi_14nm_pll_restore_state, >>> + }, >>> + .min_pll_rate = VCO_MIN_RATE, >>> + .max_pll_rate = VCO_MAX_RATE, >>> + .io_start = { 0x5e94400 }, >>> + .num_dsi_phy = 1, >>> +}; >>> + >>> const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { >>> .has_phy_lane = true, >>> .regulator_data = dsi_phy_14nm_17mA_regulators, >>>
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 9d5795c58a98..8688ed502dcf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_14nm_2290_cfgs }, { .compatible = "qcom,dsi-phy-14nm-660", .data = &dsi_phy_14nm_660_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-6125", + .data = &dsi_phy_14nm_6125_cfgs }, { .compatible = "qcom,dsi-phy-14nm-8953", .data = &dsi_phy_14nm_8953_cfgs }, #endif diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8b640d174785..ebf915f5e6c6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 3ce45b023e63..5d43c9ec69ae 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .num_dsi_phy = 2, }; +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { + .has_phy_lane = true, + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0x5e94400 }, + .num_dsi_phy = 1, +}; + const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_14nm_17mA_regulators,
SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ 3 files changed, 18 insertions(+)