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[82.31.201.19]) by smtp.gmail.com with ESMTPSA id c25-20020a7bc019000000b003f819faff24sm14089214wmb.40.2023.06.27.08.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 08:32:19 -0700 (PDT) From: Caleb Connolly Date: Tue, 27 Jun 2023 16:32:16 +0100 Subject: [PATCH 1/3] arm64: dts: qcom: c630: add panel bridge 1p2 regulator MIME-Version: 1.0 Message-Id: <20230627-c630-uart-and-1p2-reg-v1-1-b48bfb47639b@linaro.org> References: <20230627-c630-uart-and-1p2-reg-v1-0-b48bfb47639b@linaro.org> In-Reply-To: <20230627-c630-uart-and-1p2-reg-v1-0-b48bfb47639b@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Caleb Connolly X-Mailer: b4 0.13-dev-46309 X-Developer-Signature: v=1; a=openpgp-sha256; l=1883; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=+WJcNXowsCpb5IqqsxVaEzf1xlcF7Pi9NpneNQQm3q8=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBkmwEBVFBQAnyx94gDeDwfZQmv3xJsRwQG79gxm GeJnQQDBtOJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZJsBAQAKCRAFgzErGV9k tjt/D/9AsyUW+K9EtWZ9osxBp3dV1dgC5WXPYUSEMOkY0MIkUMwmaZSvioFh1vN68sQapKD9hxT XxArIV9WHMo27YEcMyPGopushrlxKOfVxZqchwpdmay8FFNfh2ov6rP1mwzmoVZhix9k+r6LYGM AEmNYq1kNBd+td/FG6KZ4gTq/nx4YyFvrDmxMH0iWbEyv66XIL/3y6G0fcGbIT6yrd3oCeeS872 oweJ0IDZwTX+wA0zKo61MfmhzRYjnnKfLStxKO1bLApydGnyynnbnjhjqpP3d9/obCfpOdUZqte vmVutCJj9Qd/YjKO7iqVL/QH1P0qNazLnI5lKM1CNtcsbaSVE3nTKxj+PHxEYHmErfd+VfIDWHY zrd8Psq2Yht7K7MTShDzfaz8r2CX6uYpU0nZqDTOAruMEfutKJKTFo2nv6FDhuhPGuc1NksWaif CM3Y1ZZPnqpKESnINsiYNVZ31LS2gK6Dp2EEOng58/yWirhI6d3SNJiTqnZ1KQ2cFYD+d5oo52z MBmHaw0nePljPAOkyPJqMo7cbAZvoTUroxApNlg5ITeip3qbmWS64pp2WvPF2ak0fyNtlu7vFx9 6vy7INiPlkF7pvR2RUQg84xHW1WZcMS2E0CU+BruMFopxMif0kn83sC5vBFUwR4unnQUzFHgm7E f5ErUgj5h3V1tug== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The VCC and VCCA supplies of the DSI<->eDP bridge are derived from vreg_l2a_1p2 and controlled by a GPIO on the PMIC. Add the regulator here so Linux can control it. Signed-off-by: Caleb Connolly --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 22a7d997cdb0..94e37e5d2177 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -80,6 +80,22 @@ adsp_mem: memory@8c600000 { }; }; + sw_edp_1p2: edp-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sw_edp_1p2_en>; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + sn65dsi86_refclk: sn65dsi86-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -425,6 +441,8 @@ sn65dsi86: bridge@2c { enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; @@ -500,6 +518,18 @@ &mss_pil { firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; +&pm8998_gpios { + /* This pin is pulled down by a fixed resistor */ + sw_edp_1p2_en: pm8998-gpio9-state { + pinconf { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = <0>; + }; + }; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable;