From patchwork Tue Sep 12 10:04:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13381253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC57FCA0EC3 for ; Tue, 12 Sep 2023 10:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233846AbjILKFQ (ORCPT ); Tue, 12 Sep 2023 06:05:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233704AbjILKFH (ORCPT ); Tue, 12 Sep 2023 06:05:07 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AFE8E6A for ; Tue, 12 Sep 2023 03:05:00 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9a63b2793ecso689801166b.2 for ; Tue, 12 Sep 2023 03:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694513099; x=1695117899; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gyROUKc805WACXkm3dpCwnosNcuRKavLVZ3ZrqpiPGc=; b=CiLIy8Z/Z1S68OCzmFuEGa+XViZbpJsLLr95kFZ5a85CeNWrg3GQAC71vCY35yyEBE IXCntkOePUTNKJx4r2cSLV8zu0kMzCCzGUMMNSXFZpqX+15LHur97sZ1/peSy65cQY/v 3MWIVfO56PlF50rG/JvY3w7Eq9pF5qB6m9PfGroDSmvNtjo4eGMyOKfsEeAqmQE2Y8GX QRfZBP2g1nf/HIVTqMZI0MJ5TG6qPZH2wKRpUy+15AYkfEeyMepSq23aR2Ip1fdpjpVq kU+S4nEGq2Ze3O/CnDPIYLLe/J/qbEkneaHYg/6ZrEI2ETR3QnTrKCQi18vJrkUivHON VMrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694513099; x=1695117899; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gyROUKc805WACXkm3dpCwnosNcuRKavLVZ3ZrqpiPGc=; b=UU5AOgWBkgzZWO1rBiw7TBDlrovwq5dBQiAi6i/Lhx0i4TTzdaXW24yFT0P5TmW4cg /AXsPwvBVMoCDG0+FgR0HjkaKPKUUVHB2I/3jHoR+3yaV5x0LBeJDRBGK8HT+kQKnCvK sMCl8yX6wwdz3y83NisF9u+Xrdwno0QJ6mNNXb7112DHf+hWCy5baNjZg/+DLnPWIaL9 NO/p4LSsvCUpUbRmiMqyc8PZZv6ixzjHIixcKuaFJmNOHShYGjuBAggrr5GbGzPgayQt H86+ghg1LL/nW6DzEmVMmY/jmULmhj0kjEVg9V9FxgY61W+9KeEWCH09EZC12MMiEGNh Pg3w== X-Gm-Message-State: AOJu0Yx+AODypaisc8WWysFznEmGthR+bPSTE3Pi0se650jVk1y7RSwe sxB9wAiGlaQrwrWfxrcEYjZCbg== X-Google-Smtp-Source: AGHT+IGbovMs0Y34FfEDEXJamv1Wxp9FDtgEmCCFofjwCrZV0B4fqYBB6Tw8h56bvhWfcL99Abm3Tw== X-Received: by 2002:a17:907:7844:b0:9a1:aea2:d18d with SMTP id lb4-20020a170907784400b009a1aea2d18dmr10259251ejc.48.1694513098897; Tue, 12 Sep 2023 03:04:58 -0700 (PDT) Received: from [10.167.154.1] (178235177248.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.248]) by smtp.gmail.com with ESMTPSA id s3-20020a170906060300b0099ce188be7fsm6592053ejb.3.2023.09.12.03.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 03:04:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 12 Sep 2023 12:04:48 +0200 Subject: [PATCH v4 06/10] drm/msm/a6xx: Send ACD state to QMP at GMU resume MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v4-6-8b3e402795c1@linaro.org> References: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694513085; l=3163; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ewvkXj7rjGrNTMhjUO9xqrzB84S4yQdvteDU7I0nOQk=; b=XAGTtQgY2PPkBKZymj4O04Lhe363VYSb9cNVhnX/N/bcK4eh9lS8l4sYOa7toyr5AOVvTRJ5D dVAVeR7XuL3Ck7eaScYzgU4BoJKADA1iZjEJRW6c0ML3CmslkCww+xz X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QMP mailbox expects to be notified of the ACD (Adaptive Clock Distribution) state. Get a handle to the mailbox at probe time and poke it at GMU resume. Since we don't fully support ACD yet, hardcode the message to "val: 0" (state = disabled). Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index c1ab48a77f45..b4a0d6b080eb 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -981,11 +981,13 @@ static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) dev_pm_opp_put(gpu_opp); } +#define GMU_ACD_STATE_MSG_LEN 36 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + char buf[GMU_ACD_STATE_MSG_LEN]; int status, ret; if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) @@ -993,6 +995,18 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) gmu->hung = false; + /* Notify AOSS about the ACD state (unimplemented for now => disable it) */ + if (!IS_ERR(gmu->qmp)) { + ret = snprintf(buf, sizeof(buf), + "{class: gpu, res: acd, val: %d}", + 0 /* Hardcode ACD to be disabled for now */); + WARN_ON(ret >= GMU_ACD_STATE_MSG_LEN); + + ret = qmp_send(gmu->qmp, buf, sizeof(buf)); + if (ret) + dev_err(gmu->dev, "failed to send GPU ACD state\n"); + } + /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); @@ -1745,6 +1759,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto detach_cxpd; } + gmu->qmp = qmp_get(gmu->dev); + if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) + return PTR_ERR(gmu->qmp); + init_completion(&gmu->pd_gate); complete_all(&gmu->pd_gate); gmu->pd_nb.notifier_call = cxpd_notifier_cb; @@ -1768,6 +1786,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) return 0; + if (!IS_ERR_OR_NULL(gmu->qmp)) + qmp_put(gmu->qmp); + detach_cxpd: dev_pm_domain_detach(gmu->cxpd, false); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 236f81a43caa..592b296aab22 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -8,6 +8,7 @@ #include #include #include +#include #include "msm_drv.h" #include "a6xx_hfi.h" @@ -96,6 +97,8 @@ struct a6xx_gmu { /* For power domain callback */ struct notifier_block pd_nb; struct completion pd_gate; + + struct qmp *qmp; }; static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)