| Message ID | 20230703175757.2425540-1-quic_srichara@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [V2] PCI: qcom: Use PARF_SLV_ADDR_SPACE_SIZE for ops_2_3_3 | expand |
On 3.07.2023 19:57, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 > 2_3_3 post_init ops. pcie slave addr size was initially set > to 0x358, but was wrongly changed to 0x168 as a part of > "PCI: qcom: Remove PCIE20_ prefix from register definitions" > Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE > and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. > > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > [V2] Fixed the 'fixes tag' correctly, subject, right macro usage > > drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..1689d072fe86 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,6 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) > u32 val; > > writel(SLV_ADDR_SPACE_SZ, > - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); > + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > > val = readl(pcie->parf + PARF_PHY_CTRL); > val &= ~PHY_TEST_PWR_DOWN;
On Mon, Jul 03, 2023 at 11:27:57PM +0530, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 > 2_3_3 post_init ops. pcie slave addr size was initially set PCIe > to 0x358, but was wrongly changed to 0x168 as a part of commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > "PCI: qcom: Remove PCIE20_ prefix from register definitions" > Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE > and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. > Commit message should be imperative. > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > [V2] Fixed the 'fixes tag' correctly, subject, right macro usage > > drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..1689d072fe86 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,6 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) > u32 val; > > writel(SLV_ADDR_SPACE_SZ, > - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); > + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); This could be wrapped in the above line itself. - Mani > > val = readl(pcie->parf + PARF_PHY_CTRL); > val &= ~PHY_TEST_PWR_DOWN; > -- > 2.34.1 >
On 7/5/2023 2:14 PM, Manivannan Sadhasivam wrote: > On Mon, Jul 03, 2023 at 11:27:57PM +0530, Sricharan Ramabadhran wrote: >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 >> 2_3_3 post_init ops. pcie slave addr size was initially set > > PCIe > >> to 0x358, but was wrongly changed to 0x168 as a part of > > commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > ok. >> "PCI: qcom: Remove PCIE20_ prefix from register definitions" >> Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE >> and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. >> > > Commit message should be imperative. ok, will send v3. > >> Without this pcie bring up on IPQ8074 is broken now. >> >> Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> [V2] Fixed the 'fixes tag' correctly, subject, right macro usage >> >> drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 4ab30892f6ef..1689d072fe86 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -43,7 +43,6 @@ >> #define PARF_PHY_REFCLK 0x4c >> #define PARF_CONFIG_BITS 0x50 >> #define PARF_DBI_BASE_ADDR 0x168 >> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ >> #define PARF_MHI_CLOCK_RESET_CTRL 0x174 >> #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 >> #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 >> @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) >> u32 val; >> >> writel(SLV_ADDR_SPACE_SZ, >> - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); >> + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > > This could be wrapped in the above line itself. sure, will post v3 Regards, Sricharan
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..1689d072fe86 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -43,7 +43,6 @@ #define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u32 val; writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN;
PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 2_3_3 post_init ops. pcie slave addr size was initially set to 0x358, but was wrongly changed to 0x168 as a part of "PCI: qcom: Remove PCIE20_ prefix from register definitions" Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. Without this pcie bring up on IPQ8074 is broken now. Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> --- [V2] Fixed the 'fixes tag' correctly, subject, right macro usage drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)