| Message ID | 20230706105045.633076-5-quic_imrashai@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Update GCC clocks for QDU1000 and QRU1000 SoCs | expand |
On 6.07.2023 12:50, Imran Shaik wrote: > Update the GCC clocks as per the latest hw version of QDU1000 and > QRU100 SoCs. > > Co-developed-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > --- > Changes since v2: > - Split the patch as per the review comments > - Newly added > > drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c > index 8df7b7983968..991fb2bc97e9 100644 > --- a/drivers/clk/qcom/gcc-qdu1000.c > +++ b/drivers/clk/qcom/gcc-qdu1000.c > @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { > }, > }; > > +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { > + .halt_reg = 0x54298, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x54298, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x54298, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_ddrss_ecpri_gsi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_ecpri_ahb_clk = { > .halt_reg = 0x3a008, > .halt_check = BRANCH_HALT_VOTED, > @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { > [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, > [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, > [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, > + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, Looks like you split it too much.. this clock is not being defined in this patch. Konrad > + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, > }; > > static const struct qcom_reset_map gcc_qdu1000_resets[] = {
On 7/15/2023 6:50 PM, Konrad Dybcio wrote: > On 6.07.2023 12:50, Imran Shaik wrote: >> Update the GCC clocks as per the latest hw version of QDU1000 and >> QRU100 SoCs. >> >> Co-developed-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> >> --- >> Changes since v2: >> - Split the patch as per the review comments >> - Newly added >> >> drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c >> index 8df7b7983968..991fb2bc97e9 100644 >> --- a/drivers/clk/qcom/gcc-qdu1000.c >> +++ b/drivers/clk/qcom/gcc-qdu1000.c >> @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { >> }, >> }; >> >> +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { >> + .halt_reg = 0x54298, >> + .halt_check = BRANCH_HALT_VOTED, >> + .hwcg_reg = 0x54298, >> + .hwcg_bit = 1, >> + .clkr = { >> + .enable_reg = 0x54298, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ddrss_ecpri_gsi_clk", >> + .parent_hws = (const struct clk_hw*[]) { >> + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_aon_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_ecpri_ahb_clk = { >> .halt_reg = 0x3a008, >> .halt_check = BRANCH_HALT_VOTED, >> @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { >> [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, >> [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, >> [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, >> + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, > Looks like you split it too much.. this clock is not being defined in this patch. > > Konrad This clock was already defined in the initial gcc changes and now adding it to gcc_qdu1000_clocks[] to register it with the clock framework. Thanks, Imran >> + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, >> }; >> >> static const struct qcom_reset_map gcc_qdu1000_resets[] = {
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 8df7b7983968..991fb2bc97e9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = {