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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:06 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:55 +0100 Subject: [PATCH v6 06/12] clk: qcom: gpucc-sm6115: Add runtime PM Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v6-6-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=1935; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=alZr67bLnwqb3yV+3Ojldc2X/6n9g3vN6yGz8GMYLR4=; b=JyJbdesuxMki5pKs7X0S5jt+C5pgrl33I4DZtUq1W2R6eKfAJkqDwXm3URq1GnvOoNT6arqBz aBv71d7sFIIDzKxhmRNM1TnbCmmZbLOXdih6zeJXXKIEFPKdpUZriD7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GPU_CC block on SM6115 is powered by the VDD_CX rail. We only need to cast an enable vote for it if the GPU blocks are in use. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index 2c2c184747b1..15cf5d63c9ad 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -443,10 +444,21 @@ MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); static int gpu_cc_sm6115_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -462,7 +474,10 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpu_cc_sm6115_driver = {