| Message ID | 20230913191957.26537-1-danila@jiaxyga.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/adreno: Add support for SM7150 SoC machine | expand |
On 13.09.2023 21:19, Danila Tikhonov wrote: > SM7150 has 5 power levels which correspond to 5 speed-bin values: 0, > 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up > to zero decimal places. > > The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses > a615 zapfw. Interesting. GMU fw comes from Qualcomm and should not(?) have any vendor modifications, btw. Can you try loading the upstream a630_gmu.bin or a619_gmu.bin from linux-firmware and seeing if anything changes? > + }, { > + .machine = "qcom,sm7150", > + .chip_ids = ADRENO_CHIP_IDS(0x06010800), > + .family = ADRENO_6XX_GEN1, > + .revn = 618, I'm not sure what Rob's stance on using revn is for values that have already been used before.. Konrad > + .fw = { > + [ADRENO_FW_SQE] = "a630_sqe.fw", > + [ADRENO_FW_GMU] = "a618_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, > + .init = a6xx_gpu_init, > + .zapfw = "a615_zap.mdt", .mbn? > + .hwcg = a615_hwcg, > + .speedbins = ADRENO_SPEEDBINS( > + { 0, 0 }, > + { 128, 1 }, > + { 146, 2 }, > + { 167, 3 }, > + { 172, 4 }, > + ), > }, { > .chip_ids = ADRENO_CHIP_IDS(0x06010800), > .family = ADRENO_6XX_GEN1, > @@ -507,6 +529,10 @@ MODULE_FIRMWARE("qcom/a530_zap.b00"); > MODULE_FIRMWARE("qcom/a530_zap.b01"); > MODULE_FIRMWARE("qcom/a530_zap.b02"); > MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); > +MODULE_FIRMWARE("qcom/a615_zap.mbt"); > +MODULE_FIRMWARE("qcom/a615_zap.b00"); > +MODULE_FIRMWARE("qcom/a615_zap.b01"); > +MODULE_FIRMWARE("qcom/a615_zap.b02"); and here too? Konrad
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fa527935ffd4..64ef9813e9ae 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -293,6 +293,28 @@ static const struct adreno_info gpulist[] = { { 157, 3 }, { 127, 4 }, ), + }, { + .machine = "qcom,sm7150", + .chip_ids = ADRENO_CHIP_IDS(0x06010800), + .family = ADRENO_6XX_GEN1, + .revn = 618, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a618_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 128, 1 }, + { 146, 2 }, + { 167, 3 }, + { 172, 4 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, @@ -507,6 +529,10 @@ MODULE_FIRMWARE("qcom/a530_zap.b00"); MODULE_FIRMWARE("qcom/a530_zap.b01"); MODULE_FIRMWARE("qcom/a530_zap.b02"); MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a615_zap.mbt"); +MODULE_FIRMWARE("qcom/a615_zap.b00"); +MODULE_FIRMWARE("qcom/a615_zap.b01"); +MODULE_FIRMWARE("qcom/a615_zap.b02"); MODULE_FIRMWARE("qcom/a619_gmu.bin"); MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin");
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0, 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up to zero decimal places. The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses a615 zapfw. Add this as machine = "qcom,sm7150", because speed-bin values are different from atoll (sc7180/sm7125). Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+)