From patchwork Thu Oct 19 02:19:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 13428174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52D8ECDB47E for ; Thu, 19 Oct 2023 02:20:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232399AbjJSCUH (ORCPT ); Wed, 18 Oct 2023 22:20:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbjJSCUC (ORCPT ); Wed, 18 Oct 2023 22:20:02 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21D109B; Wed, 18 Oct 2023 19:20:01 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39J0nOfD013360; Thu, 19 Oct 2023 02:19:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=s5m9u0ft7/a6mM7+BswRBLqRxLRZWPd2we92qi/sGso=; b=KP7PhPWy/jaCYiJgtYnbVw64BFprXRgsP8JTk4DkilVplRZzq1KUBoi4lRy0mqcl78cQ JCsZdhK+a5hXwLFHfuwcu+x7/ta1wnK79yzjDlApw/eyYc5c75BEn0CBpuViTpnXXpnj A8AQgD9cRwxy4BjYt3y9hDkX7KVTP2oF+36WtfR/sOr+HCKlO8rr142BOieY0Kg8CUbE gqc67iDdqj8sWdJRvI640EuaFnCluJTtWyGlcCV09ovIa1Q4pGYmQP0qeY2CcowjECGd xv0fmduNR02MxKQBV8FwySo43X4onK17slDEEc5iC2UrJpWM8r6oknQhL+7WUWMmzTZk Bw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3tth2f1dgm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Oct 2023 02:19:42 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39J2Jfb3001109 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Oct 2023 02:19:41 GMT Received: from hu-c-gdjako-lv.qualcomm.com (10.49.16.6) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 18 Oct 2023 19:19:40 -0700 From: Georgi Djakov To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH 2/6] iommu/arm-smmu-qcom: Add support for TBUs Date: Wed, 18 Oct 2023 19:19:19 -0700 Message-ID: <20231019021923.13939-3-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231019021923.13939-1-quic_c_gdjako@quicinc.com> References: <20231019021923.13939-1-quic_c_gdjako@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DFTd_SLrM6Zc014PUCezYFWvu7bimWYa X-Proofpoint-GUID: DFTd_SLrM6Zc014PUCezYFWvu7bimWYa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-19_02,2023-10-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310190018 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The ARM MMU-500 implements a Translation Buffer Unit (TBU) for each connected master besides a single TCU which controls and manages the address translations. Allow the Qualcomm SMMU driver to probe for any TBU devices that can provide additional debug features like triggering transactions, logging outstanding transactions, snapshot capture etc. The most basic use-case would be to get information from the TBUs and print it during a context fault. Signed-off-by: Georgi Djakov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 ++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 4 +++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7f52ac67495f..655c7f50ca84 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -1,12 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved */ #include #include #include #include +#include #include #include "arm-smmu.h" @@ -466,6 +468,16 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + /* Populate TBU devices if such are present in DT */ + if (np && of_device_is_compatible(np, "arm,mmu-500")) { + int ret; + + INIT_LIST_HEAD(&qsmmu->tbu_list); + ret = devm_of_platform_populate(smmu->dev); + if (ret) + return ERR_PTR(ret); + } + return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 593910567b88..2164a9cf3dde 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARM_SMMU_QCOM_H @@ -12,6 +12,8 @@ struct qcom_smmu { bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; + struct mutex tbu_list_lock; /* protects tbu_list */ + struct list_head tbu_list; }; enum qcom_smmu_impl_reg_offset {