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[88.207.97.46]) by smtp.googlemail.com with ESMTPSA id t11-20020a1709066bcb00b009be14e5cd54sm9626292ejs.57.2023.10.25.03.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 03:45:01 -0700 (PDT) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/3] clk: qcom: ipq6018: add USB GDSCs Date: Wed, 25 Oct 2023 12:44:10 +0200 Message-ID: <20231025104457.628109-2-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231025104457.628109-1-robimarko@gmail.com> References: <20231025104457.628109-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe. Signed-off-by: Robert Marko --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-ipq6018.c | 33 ++++++++++++++++++++++++--------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426b..2aefa2231b51b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -164,6 +164,7 @@ config IPQ_GCC_5332 config IPQ_GCC_6018 tristate "IPQ6018 Global Clock Controller" + select QCOM_GDSC help Support for global clock controller on ipq6018 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index cc20a16d8973c..9d5ee2ac012a1 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -23,6 +23,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -4691,6 +4692,22 @@ static struct clk_branch gcc_dcc_clk = { }, }; +static struct gdsc usb0_gdsc = { + .gdscr = 0x3e078, + .pd = { + .name = "usb0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb1_gdsc = { + .gdscr = 0x3f078, + .pd = { + .name = "usb1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static const struct alpha_pll_config ubi32_pll_config = { .l = 0x3e, .alpha = 0x6667, @@ -5138,6 +5155,11 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = { [GCC_Q6_AXIM_ARES] = {0x59110, 4}, }; +static struct gdsc *gcc_ipq6018_gdscs[] = { + [USB0_GDSC] = &usb0_gdsc, + [USB1_GDSC] = &usb1_gdsc, +}; + static const struct of_device_id gcc_ipq6018_match_table[] = { { .compatible = "qcom,gcc-ipq6018" }, { } @@ -5160,6 +5182,8 @@ static const struct qcom_cc_desc gcc_ipq6018_desc = { .num_resets = ARRAY_SIZE(gcc_ipq6018_resets), .clk_hws = gcc_ipq6018_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws), + .gdscs = gcc_ipq6018_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_ipq6018_gdscs), }; static int gcc_ipq6018_probe(struct platform_device *pdev) @@ -5170,15 +5194,6 @@ static int gcc_ipq6018_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* Disable SW_COLLAPSE for USB0 GDSCR */ - regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); - /* Enable SW_OVERRIDE for USB0 GDSCR */ - regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2)); - /* Disable SW_COLLAPSE for USB1 GDSCR */ - regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); - /* Enable SW_OVERRIDE for USB1 GDSCR */ - regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2)); - /* SW Workaround for UBI Huyara PLL */ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));