From patchwork Thu Nov 16 09:35:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13457733 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PXo3wun6" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D5EE9C; Thu, 16 Nov 2023 01:35:49 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AG4fYh8025328; Thu, 16 Nov 2023 09:35:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=8XCB0aouXIobVdyuL/mEIyTq2oj2Gq6MjLQndEwc/Ds=; b=PXo3wun6PjrHwCG74OK4AUIDgqVkTx8je8RYVlV/TLPPoOnKZHwGNhfwCAgIO6IQV/MQ aKKpA4C6iSnjd9siO54FLnhnGC/MHATUeUrszBydZGpW3r5Z0q+3geteFoUj0UtPxpHM mIRXrF9OaLeUvQMs3udfq8NuWi/Ml0xvehu68vnGQU7Ltn0f+g7gh5t/4AJL90axtXns 4XyaGUCAgSRaHdMEFOLnuy/V3kQVgW2NmbTo1qjBjnQds9Mqh5TqUSFU5nu8k5jC2Z/W CghI9FOg2u1XN0HlACykNm3Hh97O5NtaQMNXa9x57FzLZIs+BZ050omDfqhgDNcePmZS VA== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ud5pf18y3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 Nov 2023 09:35:23 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AG9ZJKP029204; Thu, 16 Nov 2023 09:35:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3ua2pmgd84-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 Nov 2023 09:35:19 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AG9ZJtO029189; Thu, 16 Nov 2023 09:35:19 GMT Received: from hu-devc-hyd-u20-c-new.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.147.246.70]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3AG9ZJO7029181 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 Nov 2023 09:35:19 +0000 Received: by hu-devc-hyd-u20-c-new.qualcomm.com (Postfix, from userid 3970568) id 38159220C7; Thu, 16 Nov 2023 15:05:18 +0530 (+0530) From: Rohit Agarwal To: catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, konrad.dybcio@linaro.org, arnd@arndb.de, krzysztof.kozlowski@linaro.org, neil.armstrong@linaro.org, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com, u-kumar1@ti.com, peng.fan@nxp.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@quicinc.com, Rohit Agarwal Subject: [PATCH v2 1/3] arm64: defconfig: Enable GCC for SDX75 Date: Thu, 16 Nov 2023 15:05:11 +0530 Message-Id: <20231116093513.14259-2-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231116093513.14259-1-quic_rohiagar@quicinc.com> References: <20231116093513.14259-1-quic_rohiagar@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QlWCP6ZUjsgyHupSJuK8ocwfPFCvz9J6 X-Proofpoint-ORIG-GUID: QlWCP6ZUjsgyHupSJuK8ocwfPFCvz9J6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-16_07,2023-11-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 mlxlogscore=460 mlxscore=0 spamscore=0 bulkscore=0 malwarescore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311160076 Enable Global Clock controller framework support for Qualcomm's SDX75 SoC which is required to boot to console on sdx75-idp platform. Signed-off-by: Rohit Agarwal --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..d1be1efa8a23 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1252,6 +1252,7 @@ CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y CONFIG_SDM_LPASSCC_845=m +CONFIG_SDX_GCC_75=y CONFIG_SM_CAMCC_8250=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y