| Message ID | 20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v1-4-d9340d362664@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom: Add register offsets for v6 and v7 | expand |
On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote: > > The X1E80100 platform bumps the HW version of QMP phy to v7 for USB. > Add the new PCS USB specific offsets in a dedicated header file. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h | 31 ++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h > new file mode 100644 > index 000000000000..dbb75964cef7 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h > @@ -0,0 +1,31 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_ > +#define QCOM_PHY_QMP_PCS_USB_V7_H_ > + > +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */ V7 > +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG1 0xc4 > +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG2 0xc8 > +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG3 0xcc > +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG6 0xd8 > +#define QPHY_USB_V7_PCS_REFGEN_REQ_CONFIG1 0xdc > +#define QPHY_USB_V7_PCS_USB3_POWER_STATE_CONFIG1 0x90 > +#define QPHY_USB_V7_PCS_RX_SIGDET_LVL 0x188 > +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 > +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 > +#define QPHY_USB_V7_PCS_CDR_RESET_TIME 0x1b0 > +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG1 0x1c0 > +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG2 0x1c4 > +#define QPHY_USB_V7_PCS_PCS_TX_RX_CONFIG 0x1d0 > +#define QPHY_USB_V7_PCS_EQ_CONFIG1 0x1dc > +#define QPHY_USB_V7_PCS_EQ_CONFIG5 0x1ec Some (most) of these registers do not belong here, they are the same as the generic PCS register names. Please drop them. > + > +#define QPHY_USB_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 > +#define QPHY_USB_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c > +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 > +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 Drop the _USB_ part, please, there is already PCS_USB3 prefix. > + > +#endif > > -- > 2.34.1 > >
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h new file mode 100644 index 000000000000..dbb75964cef7 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_ +#define QCOM_PHY_QMP_PCS_USB_V7_H_ + +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */ +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG1 0xc4 +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG2 0xc8 +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG3 0xcc +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG6 0xd8 +#define QPHY_USB_V7_PCS_REFGEN_REQ_CONFIG1 0xdc +#define QPHY_USB_V7_PCS_USB3_POWER_STATE_CONFIG1 0x90 +#define QPHY_USB_V7_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_USB_V7_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_USB_V7_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_USB_V7_PCS_EQ_CONFIG1 0x1dc +#define QPHY_USB_V7_PCS_EQ_CONFIG5 0x1ec + +#define QPHY_USB_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 +#define QPHY_USB_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 + +#endif
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)