| Message ID | 20231215095339.3055554-1-quic_viswanat@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC | expand |
On Fri, 15 Dec 2023 15:23:39 +0530, Vignesh Viswanathan wrote: > Add Inline Crypto Engine reg and clocks in MMC node and enable CQE > support as Inline Crypto Engine requires CQE to be enabled. > > Applied, thanks! [1/1] arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC commit: 2ae5e34d93cfe5c46229274324e1b2d176a0b516 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5f83ee42a719..7f2e5cbf3bbb 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -321,8 +321,10 @@ tcsr: syscon@1937000 { sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x07805000 0x1000>; - reg-names = "hc", "cqhci"; + reg = <0x07804000 0x1000>, + <0x07805000 0x1000>, + <0x07808000 0x2000>; + reg-names = "hc", "cqhci", "ice"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -330,9 +332,11 @@ sdhc_1: mmc@7804000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board_clk>; - clock-names = "iface", "core", "xo"; + <&xo_board_clk>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; non-removable; + supports-cqe; status = "disabled"; };
Add Inline Crypto Engine reg and clocks in MMC node and enable CQE support as Inline Crypto Engine requires CQE to be enabled. Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)