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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id t27-20020a2e8e7b000000b002d08f3640b5sm298524ljk.11.2024.03.09.05.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Mar 2024 05:31:41 -0800 (PST) From: Konrad Dybcio Date: Sat, 09 Mar 2024 14:31:10 +0100 Subject: [PATCH v2 2/2] arm64: dts: qcom: sc8280xp: Describe the PCIe SMMUv3 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231219-topic-8280_smmuv3-v2-2-c67bd3226687@linaro.org> References: <20231219-topic-8280_smmuv3-v2-0-c67bd3226687@linaro.org> In-Reply-To: <20231219-topic-8280_smmuv3-v2-0-c67bd3226687@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Johan Hovold , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709991097; l=1664; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ddTyXD0L1FluRMgAEy4AyF61rMcBg/kryptIgklrmCk=; b=MnzEy58ojuKm7m/odlIGtrimc8a/DArIDyAiRUYU5/UBseU0wxX+NzrDP2hK/VAMJBFrgm0ii LP4n5g2+g6QB1tQLGFiAgVbGGdJNibptSFC5O+QIpYSck6J0euKhxTV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= SC8280XP actually has a third SMMU, which can be seen in e.g. the IORT ACPI table and is used for the PCIe hosts. Unfortunately though, the secure firmware seems to be configured in a way such that Linux can't touch it, not even read back the ID registers. It also seems like the SMMU is configured to run in some sort of bypass mode, completely opaque to the OS. Describe it so that one can configure it when running Linux as a hypervisor (e.g with [1]) and for hardware description completeness. [1] https://github.com/TravMurav/slbounce Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a5b194813079..28edd30a9c04 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4648,6 +4648,22 @@ cci3_i2c1_sleep: cci3-i2c1-sleep-pins { }; }; + pcie_smmu: iommu@14f80000 { + compatible = "qcom,sc8280xp-smmu-v3", "arm,smmu-v3"; + reg = <0 0x14f80000 0 0x80000>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + #iommu-cells = <1>; + dma-coherent; + + /* The hypervisor prevents register access from Linux */ + status = "reserved"; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>;