| Message ID | 20240104-sm8150-dfs-support-v1-3-a5eebfdc1b12@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 | expand |
On 04/01/2024 15:23, Satya Priya Kakitapalli wrote: > Add all the available resets for the global clock controller > on sm8150. > > Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") If this is a fix, then please describe observable issue and how users are affected. See stable kernel rules document. Best regards, Krzysztof
On 1/4/2024 9:14 PM, Krzysztof Kozlowski wrote: > On 04/01/2024 15:23, Satya Priya Kakitapalli wrote: >> Add all the available resets for the global clock controller >> on sm8150. >> >> Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") > If this is a fix, then please describe observable issue and how users > are affected. See stable kernel rules document. No issues are observed as of now, just wanted to make sure all the available resets are added. I'll remove the fixes tag. > Best regards, > Krzysztof >
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 6d76fd344ddf..833e64b61e6b 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3778,6 +3778,9 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { [GCC_USB30_PRIM_BCR] = { 0xf000 }, [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, + [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, + [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, + [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; static struct gdsc *gcc_sm8150_gdscs[] = {
Add all the available resets for the global clock controller on sm8150. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/gcc-sm8150.c | 3 +++ 1 file changed, 3 insertions(+)