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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id un9-20020a170907cb8900b00a384365e3b9sm562305ejc.195.2024.02.06.10.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 10:43:56 -0800 (PST) From: Konrad Dybcio Date: Tue, 06 Feb 2024 19:43:45 +0100 Subject: [PATCH v2 12/18] clk: qcom: gcc-sm8550: Set delay for Venus CLK resets Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240105-topic-venus_reset-v2-12-c37eba13b5ce@linaro.org> References: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707245017; l=1016; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Wzt1u2nUXpu17TbhBAtUYSKbvWX7vxBCCMtjsfpido0=; b=DcjLxfc2Cefhlse0tnRH627Hek7w2VYLS5W5OTY42IWK6t0FXg4QEljQv5cx8usNri2oN4Lv0 3lWhm18CbCxBHx8445DKFDmvq4sppy1LA9N/b6BLwI4eabVQtfAv8VS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index b883dffe5f7a..4cbc728f5c72 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3276,8 +3276,8 @@ static const struct qcom_reset_map gcc_sm8550_resets[] = { [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 }, + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 }, [GCC_VIDEO_BCR] = { 0x32000 }, };